[Mesa-dev] [PATCH 4/4] i965/vs: Allocate register set once at context creation.

[Kenneth Graunke]

Now that we use a fixed set of register classes, we can set up the
register set and conflict graphs once, at context creation, rather than
on every VS compile.  This is obviously less expensive, and also what
we already do in the FS backend.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Cc: Paul Berry <stereotype441 at gmail.com>
---
 src/mesa/drivers/dri/i965/brw_context.c             | 1 +
 src/mesa/drivers/dri/i965/brw_context.h             | 3 +++
 src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 6 ++----
 3 files changed, 6 insertions(+), 4 deletions(-)

Paul,

With this patch, the vec4 register allocation stuff works like I thought.
We probably ought to move it out of brw->vs so it's obvious that it will
be shared between the VS and GS code.  Maybe to brw->vec4.

By the way, if your GS stuff introduces any new send-from-GRF messages that
aren't of length 1 or 2, you'll need to add new register classes.  Trivial.

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 44a35d1..8a12a99 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -476,6 +476,7 @@ brwCreateContext(int api,
    }
 
    brw_fs_alloc_reg_sets(brw);
+   brw_vec4_alloc_reg_set(brw);
 
    if (INTEL_DEBUG & DEBUG_SHADER_TIME)
       brw_init_shader_time(brw);
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index dae3219..8b9eb00 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1371,6 +1371,9 @@ void brw_upload_cs_urb_state(struct brw_context *brw);
  */
 void brw_fs_alloc_reg_sets(struct brw_context *brw);
 
+/* brw_vec4_reg_allocate.cpp */
+void brw_vec4_alloc_reg_set(struct brw_context *brw);
+
 /* brw_disasm.c */
 int brw_disasm (FILE *file, struct brw_instruction *inst, int gen);
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index b86b006..3dcc67d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -95,8 +95,8 @@ vec4_visitor::reg_allocate_trivial()
    return true;
 }
 
-static void
-brw_alloc_reg_set(struct brw_context *brw)
+extern "C" void
+brw_vec4_alloc_reg_set(struct brw_context *brw)
 {
    int base_reg_count = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
 
@@ -187,8 +187,6 @@ vec4_visitor::reg_allocate()
 
    calculate_live_intervals();
 
-   brw_alloc_reg_set(brw);
-
    int node_count = virtual_grf_count;
    int first_payload_node = node_count;
    node_count += payload_reg_count;
-- 
1.8.3.4