[Mesa-dev] [PATCH 05/10] i965: Use Global GTT for Sandybridge post-sync non-zero workaround.

[Kenneth Graunke]

The kernel doesn't even set up the aliasing PPGTT on Sandybridge, so any
writes marked as PPGTT will likely just get dropped on the floor.

This begs the question: is the simple act of /requesting/ a write good
enough for the workaround, or does it need to actually work?  Past
experience suggests the workaround was effective even with PPGTT
selected.  But perhaps we'll get lucky and this will help even more...

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index bc381fb..d360943 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -625,7 +625,8 @@ intel_emit_post_sync_nonzero_flush(struct brw_context *brw)
    OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
    OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
    OUT_RELOC(brw->batch.workaround_bo,
-	     I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0);
+             I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+             PIPE_CONTROL_GLOBAL_GTT_WRITE);
    OUT_BATCH(0); /* write data */
    ADVANCE_BATCH();
 
-- 
1.8.4.4