[Mesa-dev] [PATCH 05/10] i965: Use Global GTT for Sandybridge post-sync non-zero workaround.

[Daniel Vetter]

On Thu, Dec 12, 2013 at 01:26:37AM -0800, Kenneth Graunke wrote:
> The kernel doesn't even set up the aliasing PPGTT on Sandybridge, so any
> writes marked as PPGTT will likely just get dropped on the floor.

Ermh, aliasing ppgtt is enabled on snb. But the CS write stuff is broken
and will always land in the global gtt anyway, hence why it's crucial to
set the write domain to DOMAIN_INSTRUCTION. Otherwise the kernel w/a
doesn't kick in and you write to the scratch page. btw we have a kernel
param to figure out whether you should target ppgtt or not.
> 
> This begs the question: is the simple act of /requesting/ a write good
> enough for the workaround, or does it need to actually work?  Past
> experience suggests the workaround was effective even with PPGTT
> selected.  But perhaps we'll get lucky and this will help even more...
> 
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

See above, it doesn't really matter on snb (and strictly speaking the
ppgtt selector is the right thing to do anyway on all kernels mesa
supports still). On later generations the hw ignores this bit and forces
ppgtt anyway.

Since we do the exact same thing in the pipe_control i-g-t testcase (and
that one checks whether the write lands) for gen6&7, this is

Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch>

> ---
>  src/mesa/drivers/dri/i965/intel_batchbuffer.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> index bc381fb..d360943 100644
> --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> @@ -625,7 +625,8 @@ intel_emit_post_sync_nonzero_flush(struct brw_context *brw)
>     OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
>     OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
>     OUT_RELOC(brw->batch.workaround_bo,
> -	     I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0);
> +             I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
> +             PIPE_CONTROL_GLOBAL_GTT_WRITE);
>     OUT_BATCH(0); /* write data */
>     ADVANCE_BATCH();
>  
> -- 
> 1.8.4.4
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch