[Mesa-dev] [wip 2/2] i965/gen7+ Remove tile_x and tile_y dependency in BLORP

[Topi Pohjolainen]

From: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>

GEN7+-specific hw-support. This can be copied over to GEN8/Broadwell with few
modifications.

v2 (Topi):

I looked into the piglit failures and compared the surface
setup logic into "gen7_update_texture/renderbuffer_surface()".
Here are some of my findings:

Use the 'is_render_target' argument instead of introducing its
negate 'is_source'.

Keep on using the surface dimensions instead of logical for w-tiled
stencil. Piglit tests revealed cases where the logical dimensions
were 16x16 but dimensions set for the surface were 8x32 and 16x64,
for example.

  ext_framebuffer_multisample-accuracy 4 color depthstencil

Further examination of piglit tests highlighted cases where the
"intel_mipmap_tree::num_samples" is greater than one. In such a
case physical dimensions equaled the dimensions set for the surface
but I thought safer to keep on using the surface dimensions instead
(such as before).

Added the layer settings mimicking the logic in
"gen7_update_renderbuffer_surface()" - needed for 2d_array cases.

  gl-3.2-layered-rendering-clear-color-all-types 2d_array single_level
  gl-3.2-layered-rendering-clear-color-all-types 2d_array mipmapped

Added support for clearing texture_3d - surface type and surface
depth settings.

  gl-3.2-layered-rendering-clear-color-all-types 3d mipmapped

Blitting from layers other zero for texture_3d needs some more work.
I modified 'brw_blorp_blit_miptrees()' to resolve the surface type
the same way I did for clear. That, however, was not sufficient.
If I'm not mistaken one would also need changes in the sampler
message to tell the sampler which layer is to be accessed.

  gl-3.2-layered-rendering-blit -fbo -auto

Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
---
 src/mesa/drivers/dri/i965/gen7_blorp.cpp | 36 +++++++++++++++++++-------------
 1 file changed, 22 insertions(+), 14 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index c687454..c310120 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -142,15 +142,14 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
                               bool is_render_target)
 {
    uint32_t wm_surf_offset;
-   uint32_t width = surface->width;
-   uint32_t height = surface->height;
+   uint32_t width = surface->mt->logical_width0;
+   uint32_t height = surface->mt->logical_height0;
    /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
     * color surfaces, width and height are measured in pixels; we don't need
     * to divide them by 2 as we do for Gen6 (see
     * gen6_blorp_emit_surface_state).
     */
    struct intel_region *region = surface->mt->region;
-   uint32_t tile_x, tile_y;
    const uint8_t mocs = GEN7_MOCS_L3;
 
    uint32_t tiling = surface->map_stencil_as_y_tiled
@@ -160,7 +159,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
    memset(surf, 0, 8 * 4);
 
-   surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
+   surf[0] = surface->surftype << BRW_SURFACE_TYPE_SHIFT |
              surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
              gen7_surface_tiling_mode(tiling);
 
@@ -175,27 +174,36 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
       surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
 
    /* reloc */
-   surf[1] =
-      surface->compute_tile_offsets(&tile_x, &tile_y) + region->bo->offset;
+   surf[1] = region->bo->offset;
 
-   /* Note that the low bits of these fields are missing, so
-    * there's the possibility of getting in trouble.
+   /* W-tiled stencil buffers that are treated as Y-tiled have corresponding
+    * Y-tiling compatible dimensions in the surface - use them instead of
+    * logical.
+    * Multi-sampled surfaces are also special, use the surface dimensions
+    * instead.
     */
-   assert(tile_x % 4 == 0);
-   assert(tile_y % 2 == 0);
-   surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
-             SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET) |
-             SET_FIELD(mocs, GEN7_SURFACE_MOCS);
+   if (surface->map_stencil_as_y_tiled || surface->mt->num_samples) {
+      width = surface->width;
+      height = surface->height;
+   }
 
    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 
+   surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS) | surface->level;
+   if (!is_render_target)
+      surf[5] |= SET_FIELD(surface->level, GEN7_SURFACE_MIN_LOD);
+
    uint32_t pitch_bytes = region->pitch;
    if (surface->map_stencil_as_y_tiled)
       pitch_bytes *= 2;
-   surf[3] = pitch_bytes - 1;
+   surf[3] = SET_FIELD(surface->mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) |
+             (pitch_bytes - 1);
 
    surf[4] = gen7_surface_msaa_bits(surface->num_samples, surface->msaa_layout);
+   if (is_render_target)
+      surf[4] |= (surface->layer << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT);
+
    if (surface->mt->mcs_mt) {
       gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt,
                                 is_render_target);
-- 
1.8.3.1