[Mesa-dev] [RFC PATCH 04/12] i965: Add MI_RS_STORE_DATA_IMM workaround for 3DPRIMITIVE commands

[Abdiel Janulgue]

Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
---
 src/mesa/drivers/dri/i965/brw_draw.c |   14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 5730eed..436077b 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -256,6 +256,20 @@ static void gen7_emit_prim(struct brw_context *brw,
       intel_batchbuffer_emit_mi_flush(intel);
    }
 
+   /* If resource streamer is enabled, an MI_RS_STORE_DATA_IMM with Resource
+    * Streamer Flush set must be programmed prior to a 3DPRIMITIVE command.
+    */
+   if (intel->is_haswell) {
+      BEGIN_BATCH(4);
+      OUT_BATCH(MI_RS_STORE_DATA_IMM |
+                (1 << 21) |  /* rs flush */
+                (4 - 2));
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      ADVANCE_BATCH();
+   }
+
    BEGIN_BATCH(7);
    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
    OUT_BATCH(hw_prim | vertex_access_type);
-- 
1.7.9.5