[Mesa-dev] [PATCH 1/2] i965/gen7: Add defines for Memory Object Control State

[Chad Versace]

For Ivybridge and Haswell.

Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
---
 src/mesa/drivers/dri/i965/brw_defines.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index fa257ac..ebce8b9 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -550,6 +550,8 @@
 #define BRW_SURFACE_Y_OFFSET_MASK		INTEL_MASK(23, 20)
 #define GEN7_SURFACE_MIN_LOD_SHIFT              4
 #define GEN7_SURFACE_MIN_LOD_MASK               INTEL_MASK(7, 4)
+#define GEN7_SURFACE_MOCS_SHIFT                 16
+#define GEN7_SURFACE_MOCS_MASK                  INTEL_MASK(19, 16)
 
 /* Surface state DW6 */
 #define GEN7_SURFACE_MCS_ENABLE                 (1 << 0)
@@ -1727,6 +1729,24 @@ enum brw_wm_barycentric_interp_mode {
  */
 #define BRW_MAX_NUM_BUFFER_ENTRIES	(1 << 27)
 
+/* Memory Object Control State, Gen7 */
+/* L3 Cacheability Control */
+#define GEN7_MOCS_L3_UNCACHEABLE                0
+#define GEN7_MOCS_L3_CACHEABLE                  1
+/* LCC Cacheability Control */
+#define GEN7_MOCS_LCC_USE_PTE                   (0 << 1)
+#define GEN7_MOCS_LCC_CACHEABLE                 (1 << 1)
+
+/* Memory Object Control State, Haswell */
+/* L3 Cacheability Control */
+#define HSW_MOCS_L3_UNCACHEABLE                 0
+#define HSW_MOCS_L3_CACHEABLE                   1
+/* LCC Cacheability Control */
+#define HSW_MOCS_LCC_USE_PTE                    (0 << 1)
+#define HSW_MOCS_LCC_UNCACHEABLE                (1 << 1)
+#define HSW_MOCS_LCC_WB_TO_LLC_ELLC             (2 << 1)
+#define HSW_MOCS_LCC_WB_TO_ELLC                 (3 << 1)
+
 #include "intel_chipset.h"
 
 #endif
-- 
1.8.3.1