[Mesa-dev] [PATCH 0/2] i965/hsw: Set MOCS to L3_CACHEABLE

[Chad Versace]

Gives +5.68% on 1920x1080 Xonotic on Haswell GT2.

Performance Measurements
========================
system-info {
    gpu: haswell_m_gt2 0x0416 rev05
    arch: x86_64
    kernel: 3.9.9-1-ARCH (Archlinux)
    xf86-video-intel: 2.12.11-1 (Archlinux)
    libdrm: 2.4.46-2 (Archlinux)
}

test {
    name: pts/xonotic-1.3.1 1920x1080 quality=high
    delta: +5.68152% +/- 0.653452% (student's t) at 95% confidence
    n: 3
    pooled-s: 0.288297
    mesa-base: master-00d32cd
}


Chad Versace (2):
  i965/gen7: Add defines for Memory Object Control State
  i965/hsw: Set MOCS to L3_CACHEABLE for some packets

 src/mesa/drivers/dri/i965/brw_defines.h           | 20 ++++++++++++++
 src/mesa/drivers/dri/i965/brw_draw_upload.c       |  3 +++
 src/mesa/drivers/dri/i965/brw_misc_state.c        | 11 +++++++-
 src/mesa/drivers/dri/i965/gen6_blorp.cpp          | 14 +++++++++-
 src/mesa/drivers/dri/i965/gen7_blorp.cpp          | 32 ++++++++++++++++++++---
 src/mesa/drivers/dri/i965/gen7_misc_state.c       | 13 +++++++--
 src/mesa/drivers/dri/i965/gen7_vs_state.c         | 10 ++++++-
 src/mesa/drivers/dri/i965/gen7_wm_state.c         | 10 ++++++-
 src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 18 ++++++++++++-
 9 files changed, 120 insertions(+), 11 deletions(-)

-- 
1.8.3.1