[Mesa-dev] [PATCH] i965: Don't disable unused shader stages from BLORP.

[Kenneth Graunke]

As of commit 6c966ccf07bcaf64fba1a9b699440c30dc96e732, we disable these
stages once on start up and never have to do it again.

Furthermore, redundant disabling is harmful: emitting multiple
3DSTATE_CONSTANT_* packets without an intervening 3DPRIMITIVE is
illegal.  If the first operation that occurs after context creation
uses BLORP, we would emit two 3DSTATE_CONSTANT_{GS,HS,DS} packets and
potentially hang the GPU.

Cc: Vedran Rodic <vrodic at gmail.com>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
 src/mesa/drivers/dri/i965/gen7_blorp.cpp | 116 -------------------------------
 1 file changed, 116 deletions(-)

Vedran,

Can you try this patch and see if it solves your GPU hang issues?  I still
haven't been able to reproduce it, but I believe I may just be getting lucky.

Thanks!
 --Ken

diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index aa9a3ef..54e2342 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -307,118 +307,6 @@ gen7_blorp_emit_vs_disable(struct brw_context *brw,
 }
 
 
-/* 3DSTATE_HS
- *
- * Disable the hull shader.
- */
-static void
-gen7_blorp_emit_hs_disable(struct brw_context *brw,
-                           const brw_blorp_params *params)
-{
-   struct intel_context *intel = &brw->intel;
-
-   BEGIN_BATCH(7);
-   OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
-
-   BEGIN_BATCH(7);
-   OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
-}
-
-
-/* 3DSTATE_TE
- *
- * Disable the tesselation engine.
- */
-static void
-gen7_blorp_emit_te_disable(struct brw_context *brw,
-                           const brw_blorp_params *params)
-{
-   struct intel_context *intel = &brw->intel;
-
-   BEGIN_BATCH(4);
-   OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
-}
-
-
-/* 3DSTATE_DS
- *
- * Disable the domain shader.
- */
-static void
-gen7_blorp_emit_ds_disable(struct brw_context *brw,
-                           const brw_blorp_params *params)
-{
-   struct intel_context *intel = &brw->intel;
-
-   BEGIN_BATCH(7);
-   OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
-
-   BEGIN_BATCH(6);
-   OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
-}
-
-/* 3DSTATE_GS
- *
- * Disable the geometry shader.
- */
-static void
-gen7_blorp_emit_gs_disable(struct brw_context *brw,
-                           const brw_blorp_params *params)
-{
-   struct intel_context *intel = &brw->intel;
-
-   BEGIN_BATCH(7);
-   OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
-
-   BEGIN_BATCH(7);
-   OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
-}
-
 /* 3DSTATE_STREAMOUT
  *
  * Disable streamout.
@@ -880,10 +768,6 @@ gen7_blorp_exec(struct intel_context *intel,
       sampler_offset = gen7_blorp_emit_sampler_state(brw, params);
    }
    gen7_blorp_emit_vs_disable(brw, params);
-   gen7_blorp_emit_hs_disable(brw, params);
-   gen7_blorp_emit_te_disable(brw, params);
-   gen7_blorp_emit_ds_disable(brw, params);
-   gen7_blorp_emit_gs_disable(brw, params);
    gen7_blorp_emit_streamout_disable(brw, params);
    gen6_blorp_emit_clip_disable(brw, params);
    gen7_blorp_emit_sf_config(brw, params);
-- 
1.8.3