[Mesa-dev] [PATCH 3/6] i965: add SHADER_OPCODE_TG4

[Chris Forbes]

Adds the Gen7 message IDs, a new SHADER_OPCODE_TG4 pseudo-op, and
low-level support for emitting it via generate_tex().

Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
---
 src/mesa/drivers/dri/i965/brw_defines.h     | 3 +++
 src/mesa/drivers/dri/i965/brw_fs.cpp        | 4 +++-
 src/mesa/drivers/dri/i965/brw_fs_emit.cpp   | 5 +++++
 src/mesa/drivers/dri/i965/brw_vec4.cpp      | 3 ++-
 src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | 4 ++++
 5 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 3d07c36..9aeefa4 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -712,6 +712,7 @@ enum opcode {
    FS_OPCODE_TXB,
    SHADER_OPCODE_TXF_MS,
    SHADER_OPCODE_LOD,
+   SHADER_OPCODE_TG4,
 
    SHADER_OPCODE_SHADER_TIME_ADD,
 
@@ -898,8 +899,10 @@ enum brw_message_target {
 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE  6
 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD           7
+#define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4      8
 #define GEN5_SAMPLER_MESSAGE_LOD                 9
 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO      10
+#define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO   17
 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS       29
 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS       30
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index cba1167..5ae9ffe 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -339,7 +339,8 @@ fs_inst::is_tex()
            opcode == SHADER_OPCODE_TXF_MS ||
            opcode == SHADER_OPCODE_TXL ||
            opcode == SHADER_OPCODE_TXS ||
-           opcode == SHADER_OPCODE_LOD);
+           opcode == SHADER_OPCODE_LOD ||
+           opcode == SHADER_OPCODE_TG4);
 }
 
 bool
@@ -731,6 +732,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
    case SHADER_OPCODE_TXD:
    case SHADER_OPCODE_TXF:
    case SHADER_OPCODE_TXF_MS:
+   case SHADER_OPCODE_TG4:
    case SHADER_OPCODE_TXL:
    case SHADER_OPCODE_TXS:
    case SHADER_OPCODE_LOD:
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
index a729569..c09d259 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
@@ -401,6 +401,10 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
       case SHADER_OPCODE_LOD:
          msg_type = GEN5_SAMPLER_MESSAGE_LOD;
          break;
+      case SHADER_OPCODE_TG4:
+         assert(intel->gen >= 7);
+         msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
+         break;
       default:
 	 assert(!"not reached");
 	 break;
@@ -1274,6 +1278,7 @@ fs_generator::generate_code(exec_list *instructions)
       case SHADER_OPCODE_TXL:
       case SHADER_OPCODE_TXS:
       case SHADER_OPCODE_LOD:
+      case SHADER_OPCODE_TG4:
 	 generate_tex(inst, dst, src[0]);
 	 break;
       case FS_OPCODE_DDX:
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 184eff9..3919866 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -148,7 +148,8 @@ vec4_instruction::is_tex()
 	   opcode == SHADER_OPCODE_TXF ||
 	   opcode == SHADER_OPCODE_TXF_MS ||
 	   opcode == SHADER_OPCODE_TXL ||
-	   opcode == SHADER_OPCODE_TXS);
+	   opcode == SHADER_OPCODE_TXS ||
+	   opcode == SHADER_OPCODE_TG4);
 }
 
 void
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index cb49a04..7938c14 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -298,6 +298,9 @@ vec4_generator::generate_tex(vec4_instruction *inst,
       case SHADER_OPCODE_TXS:
 	 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
 	 break;
+      case SHADER_OPCODE_TG4:
+         msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
+         break;
       default:
 	 assert(!"should not get here: invalid VS texture opcode");
 	 break;
@@ -654,6 +657,7 @@ vec4_generator::generate_vs_instruction(vec4_instruction *instruction,
    case SHADER_OPCODE_TXF_MS:
    case SHADER_OPCODE_TXL:
    case SHADER_OPCODE_TXS:
+   case SHADER_OPCODE_TG4:
       generate_tex(inst, dst, src[0]);
       break;
 
-- 
1.8.2