[Mesa-dev] [PATCH] i965: Fix vertical alignment for multisampled buffers.

Eric Anholt eric at anholt.net
Tue Nov 12 14:46:04 PST 2013

Paul Berry <stereotype441 at gmail.com> writes:

> From the Sandy Bridge PRM, Vol 1 Part 1 (Alignment Unit
> Size):
>     j [vertical alignment] = 4 for any render target surface is
>     multisampled (4x)
> From the Ivy Bridge PRM, Vol 4 Part 1 (SURFACE_STATE for most
> messages), under the "Surface Vertical Alignment" heading:
>     This field is intended to be set to VALIGN_4 if the surface was
>     rendered as a depth buffer, for a multisampled (4x) render target,
>     or for a multisampled (8x) render target, since these surfaces
>     support only alignment of 4.
> Back in 2012 when we added multisampling support to the i965 driver,
> we forgot to update the logic for computing the vertical alignment, so
> we were often using a vertical alignment of 2 for multisampled
> buffers, leading to subtle rendering errors.
> Note that the specs also require a vertical alignment of 4 for all
> Y-tiled render target surfaces; I plan to address that in a separate
> patch.
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53077

Now I want to rush home and test my rb-miplevels code on snb again,
which was failing on some msaa tests.

CC stable, and:

Reviewed-by: Eric Anholt <eric at anholt.net>
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