[Mesa-dev] [PATCH] R600/SI: Implement spilling of SGPRs v4

[Michel Dänzer]

On Mon, 2013-11-25 at 23:32 -0500, Tom Stellard wrote:
> From: Tom Stellard <thomas.stellard at amd.com>
> 
> SGPRs are spilled into VGPRs using the {READ,WRITE}LANE_B32 instructions.
> 
> v2:
>   - Fix encoding of Lane Mask
>   - Use correct register flags, so we don't overwrite the low dword
>     when restoring multi-dword registers.
> 
> v3:
>   - Register spilling seems to hang the GPU, so replace all shaders
>     that need spilling with a dummy shader.
> 
> v4:
>   - Fix *LANE definitions
>   - Change destination reg class for 32-bit SMRD instructions
> 
> https://bugs.freedesktop.org/show_bug.cgi?id=71285
> 
> NOTE: This is a candidate for the 3.4 branch.

Tested-by: Michel Dänzer <michel.daenzer at amd.com>


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Earthling Michel Dänzer            |                  http://www.amd.com
Libre software enthusiast          |                Mesa and X developer