[Mesa-dev] [PATCH] R600/SI: Implement spilling of SGPRs v4
Tom Stellard
tom at stellard.net
Tue Nov 26 10:34:24 PST 2013
Hi,
Here is an updated version of the register spilling patches with a fix
for Serious Sam. I've also split the patch into two as Christian
suggested.
-Tom
On Tue, Nov 26, 2013 at 11:18:56AM +0100, Christian König wrote:
> Am 26.11.2013 05:32, schrieb Tom Stellard:
> > From: Tom Stellard <thomas.stellard at amd.com>
> >
> > SGPRs are spilled into VGPRs using the {READ,WRITE}LANE_B32 instructions.
> >
> > v2:
> > - Fix encoding of Lane Mask
> > - Use correct register flags, so we don't overwrite the low dword
> > when restoring multi-dword registers.
> >
> > v3:
> > - Register spilling seems to hang the GPU, so replace all shaders
> > that need spilling with a dummy shader.
> >
> > v4:
> > - Fix *LANE definitions
> > - Change destination reg class for 32-bit SMRD instructions
> >
> > https://bugs.freedesktop.org/show_bug.cgi?id=71285
> >
> >
>
> [SNIP]
>
> >
> > -defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SReg_32>;
> > +// We are using the SGPR_32 and not the SReg_32 register class for 32-bit
> > +// SMRD instructions, because the SGPR_32 register class does not include M0
> > +// and writing to M0 from an SMRD instruction will hang the GPU.
> > +defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>;
> > defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>;
> > defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>;
> > defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>;
> > defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>;
> >
> > defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
> > - 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SReg_32
> > + 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32
> > >;
>
> This change looks like it might want to go into a separate patch, apart
> from that the patch is:
>
> Reviewed-by: Christian König <christian.koenig at amd.com>
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