[Mesa-dev] [PATCH 4/7] i965: Add SHADER_OPCODE_TG4_OFFSET for gather with nonconstant offsets.

[Chris Forbes]

The generator code ends up clearer this way than if we had to sniff
via mlen. Implemented via the gather4_po message in hardware, which is
present in Gen7 and later.

Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
---
 src/mesa/drivers/dri/i965/brw_defines.h          | 1 +
 src/mesa/drivers/dri/i965/brw_fs.cpp             | 1 +
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp   | 8 +++++++-
 src/mesa/drivers/dri/i965/brw_shader.cpp         | 5 ++++-
 src/mesa/drivers/dri/i965/brw_vec4.cpp           | 1 +
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 7 ++++++-
 6 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index c1e7f31..f1ea736 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -771,6 +771,7 @@ enum opcode {
    SHADER_OPCODE_TXF_MS,
    SHADER_OPCODE_LOD,
    SHADER_OPCODE_TG4,
+   SHADER_OPCODE_TG4_OFFSET,
 
    SHADER_OPCODE_SHADER_TIME_ADD,
 
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 48ee149..ad87b5f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -728,6 +728,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
    case SHADER_OPCODE_TXF:
    case SHADER_OPCODE_TXF_MS:
    case SHADER_OPCODE_TG4:
+   case SHADER_OPCODE_TG4_OFFSET:
    case SHADER_OPCODE_TXL:
    case SHADER_OPCODE_TXS:
    case SHADER_OPCODE_LOD:
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 4159773..dda14aa 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -435,6 +435,10 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
          assert(brw->gen >= 6);
          msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
          break;
+      case SHADER_OPCODE_TG4_OFFSET:
+         assert(brw->gen >= 7);
+         msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
+         break;
       default:
 	 assert(!"not reached");
 	 break;
@@ -522,7 +526,8 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
       src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
    }
 
-   uint32_t surface_index = inst->opcode == SHADER_OPCODE_TG4
+   uint32_t surface_index = (inst->opcode == SHADER_OPCODE_TG4 ||
+      inst->opcode == SHADER_OPCODE_TG4_OFFSET)
       ? SURF_INDEX_GATHER_TEXTURE(inst->sampler)
       : SURF_INDEX_TEXTURE(inst->sampler);
 
@@ -1473,6 +1478,7 @@ fs_generator::generate_code(exec_list *instructions)
       case SHADER_OPCODE_TXS:
       case SHADER_OPCODE_LOD:
       case SHADER_OPCODE_TG4:
+      case SHADER_OPCODE_TG4_OFFSET:
 	 generate_tex(inst, dst, src[0]);
 	 break;
       case FS_OPCODE_DDX:
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 19500d1..6b37f58 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -439,6 +439,8 @@ brw_instruction_name(enum opcode op)
       return "txf_ms";
    case SHADER_OPCODE_TG4:
       return "tg4";
+   case SHADER_OPCODE_TG4_OFFSET:
+      return "tg4_offset";
 
    case FS_OPCODE_DDX:
       return "ddx";
@@ -535,7 +537,8 @@ backend_instruction::is_tex()
            opcode == SHADER_OPCODE_TXL ||
            opcode == SHADER_OPCODE_TXS ||
            opcode == SHADER_OPCODE_LOD ||
-           opcode == SHADER_OPCODE_TG4);
+           opcode == SHADER_OPCODE_TG4 ||
+           opcode == SHADER_OPCODE_TG4_OFFSET);
 }
 
 bool
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 149a1a0..b0688c1 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -271,6 +271,7 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
    case SHADER_OPCODE_TXF_MS:
    case SHADER_OPCODE_TXS:
    case SHADER_OPCODE_TG4:
+   case SHADER_OPCODE_TG4_OFFSET:
       return inst->header_present ? 1 : 0;
    default:
       assert(!"not reached");
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 67af0dd..cb83231 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -311,6 +311,9 @@ vec4_generator::generate_tex(vec4_instruction *inst,
       case SHADER_OPCODE_TG4:
          msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
          break;
+      case SHADER_OPCODE_TG4_OFFSET:
+         msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
+         break;
       default:
 	 assert(!"should not get here: invalid VS texture opcode");
 	 break;
@@ -385,7 +388,8 @@ vec4_generator::generate_tex(vec4_instruction *inst,
       break;
    }
 
-   uint32_t surface_index = inst->opcode == SHADER_OPCODE_TG4
+   uint32_t surface_index = (inst->opcode == SHADER_OPCODE_TG4 ||
+      inst->opcode == SHADER_OPCODE_TG4_OFFSET)
       ? SURF_INDEX_VEC4_GATHER_TEXTURE(inst->sampler)
       : SURF_INDEX_VEC4_TEXTURE(inst->sampler);
 
@@ -1071,6 +1075,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
    case SHADER_OPCODE_TXL:
    case SHADER_OPCODE_TXS:
    case SHADER_OPCODE_TG4:
+   case SHADER_OPCODE_TG4_OFFSET:
       generate_tex(inst, dst, src[0]);
       break;
 
-- 
1.8.4