[Mesa-dev] [PATCH V2 07/12] i965: Add FS backend for builtin gl_SamplePosition

[Anuj Phogat]

On Tue, Oct 29, 2013 at 12:36 AM, Eric Anholt <eric at anholt.net> wrote:

> Anuj Phogat <anuj.phogat at gmail.com> writes:
>
> > V2:
> >    - Update comments.
> >    - Make changes to support simd16 mode.
> >    - Add compute_pos_offset variable in brw_wm_prog_key.
> >    - Add variable uses_omask in brw_wm_prog_data.
> >
> > Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
>
> > +fs_reg *
> > +fs_visitor::emit_samplepos_setup(ir_variable *ir)
> > +{
> > +   assert(brw->gen >= 6);
> > +   assert(ir->type == glsl_type::vec2_type);
> > +
> > +   this->current_annotation = "compute sample position";
> > +   fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
> > +   fs_reg pos = *reg;
> > +   fs_reg int_sample_x = fs_reg(this, glsl_type::int_type);
> > +   fs_reg int_sample_y = fs_reg(this, glsl_type::int_type);
> > +
> > +   /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or
> SIMD16
> > +    * mode will be enabled.
> > +    *
> > +    * From the Ivy Bridge PRM, volume 2 part 1, page 344:
> > +    * R31.1:0         Position Offset X/Y for Slot[3:0]
> > +    * R31.3:2         Position Offset X/Y for Slot[7:4]
> > +    * .....
> > +    *
> > +    * The X, Y sample positions come in as bytes in  thread payload.
> So, read
> > +    * the positions using vstride=16, width=8, hstride=2.
> > +    */
> > +   struct brw_reg sample_pos_reg =
> > +      stride(retype(brw_vec1_grf(c->sample_pos_reg, 0),
> > +                    BRW_REGISTER_TYPE_B), 16, 8, 2);
> > +
> > +   emit(MOV(int_sample_x, fs_reg(sample_pos_reg)));
> > +   /* Compute gl_SamplePosition.x */
> > +   compute_sample_position(pos, int_sample_x);
> > +   pos.reg_offset += dispatch_width / 8;
>
> I noticed this during a brief glance at the series: You're incrementing
> pos's reg_offset by 2 in the dispatch_width == 16 case, but afaik
> ir->type is just a vec2.  If you want to access the second half of a
> vec2 GRF, that's just pos.reg_offset++ regardless of whether you're in 8
> or 16 mode.
>
Thanks for noticing this Eric. I'll fix it. Code generated for SIMD16 is
still
untested because of some unexpected issues I faced with "SIMD16 only"
dispatch. That's why we're enabling 'SIMD8 only' dispatch in this series.
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