[Mesa-dev] [PATCH] i965/gen7.5: Fix lower bound on number of VS URB entries.

[Chad Versace]

On 08/31/2013 10:34 PM, Paul Berry wrote:
> Haswell GT2 and GT3 require the number of vertex shader URB entries to
> be at least 64, not 32.
>
> At the moment, we always meet this requirement automatically, because
> in the absence of a geometry shader, we assign all available URB space
> to the vertex shader.  But when we turn on support for geometry
> shaders, this lower limit will become important.
> ---
>   src/mesa/drivers/dri/i965/brw_context.c | 7 +++++++
>   src/mesa/drivers/dri/i965/brw_context.h | 1 +
>   src/mesa/drivers/dri/i965/gen6_urb.c    | 2 +-
>   src/mesa/drivers/dri/i965/gen7_urb.c    | 7 ++++---
>   4 files changed, 13 insertions(+), 4 deletions(-)

Reviewed-by: Chad Versace <chad.versace at linux.intel.com>