[Mesa-dev] [PATCH 2/3] i965/gen7: Set MOCS L3 cacheability for IVB/BYT

[Ville Syrjälä]

On Thu, Aug 15, 2013 at 10:39:31PM +0200, Vedran Rodic wrote:
> > We do have the set_caching ioctl. It's enough to flip the PTEs to UC and
> > let MOCS manage things. I actually did a few experiments on my IVB. I
> > made all Mesa's buffers UC via PTEs by patching libdrm to change the
> > cache mode of each bo after allocation. Then I fiddled with the MOCS
> > LLC bits in various ways. It definitely has an effect, sometimes making
> > things slower, sometimes faster. xonotic again seemed to benefit. IIRC
> > leaving everything LLC uncached was actually the fastest (w/ high quality
> > at least) so we may be thrashing the LLC a bit there. But eg. reaction
> > quake regressed quite a lot if most things were left as UC.
> 
> Can you share the libdrm patch?

Sorry, forgot to reply.

Here's the patch if you're still interested.

>From 47f51b19137603dccaa4fcb2a703d56335c292fe Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala at linux.intel.com>
Date: Wed, 14 Aug 2013 15:12:29 +0300
Subject: [PATCH] make bos uncached in PTEs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 intel/intel_bufmgr_gem.c | 60 ++++++++++++++++++++++++++++++++++++++++++------
 1 file changed, 53 insertions(+), 7 deletions(-)

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index f98f7a7..32ff260 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -243,6 +243,10 @@ drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
 			    uint32_t * swizzle_mode);
 
 static int
+drm_intel_gem_bo_set_caching_internal(drm_intel_bo *bo,
+				      uint32_t cache_mode);
+
+static int
 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
 				     uint32_t tiling_mode,
 				     uint32_t stride);
@@ -695,6 +699,7 @@ retry:
 				drm_intel_gem_bo_free(&bo_gem->bo);
 				goto retry;
 			}
+
 		}
 	}
 	pthread_mutex_unlock(&bufmgr_gem->lock);
@@ -761,9 +766,16 @@ drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
 				  unsigned long size,
 				  unsigned int alignment)
 {
-	return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
-					       BO_ALLOC_FOR_RENDER,
-					       I915_TILING_NONE, 0);
+	drm_intel_bo *bo;
+
+	bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
+					     BO_ALLOC_FOR_RENDER,
+					     I915_TILING_NONE, 0);
+
+	if (bo)
+		drm_intel_gem_bo_set_caching_internal(bo, I915_CACHEING_NONE);
+
+	return bo;
 }
 
 static drm_intel_bo *
@@ -772,8 +784,15 @@ drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
 		       unsigned long size,
 		       unsigned int alignment)
 {
-	return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
-					       I915_TILING_NONE, 0);
+	drm_intel_bo *bo;
+
+	bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
+					     I915_TILING_NONE, 0);
+
+	if (bo)
+		drm_intel_gem_bo_set_caching_internal(bo, I915_CACHEING_CACHED);
+
+	return bo;
 }
 
 static drm_intel_bo *
@@ -784,6 +803,7 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
 	drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
 	unsigned long size, stride;
 	uint32_t tiling;
+	drm_intel_bo *bo;
 
 	do {
 		unsigned long aligned_y, height_alignment;
@@ -824,8 +844,13 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
 	if (tiling == I915_TILING_NONE)
 		stride = 0;
 
-	return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
-					       tiling, stride);
+	bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
+					     tiling, stride);
+
+	if (bo)
+		drm_intel_gem_bo_set_caching_internal(bo, I915_CACHEING_NONE);
+
+	return bo;
 }
 
 /**
@@ -2363,6 +2388,27 @@ drm_intel_gem_bo_unpin(drm_intel_bo *bo)
 }
 
 static int
+drm_intel_gem_bo_set_caching_internal(drm_intel_bo *bo,
+				      uint32_t cache_mode)
+{
+	drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
+	drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
+	struct drm_i915_gem_cacheing set_caching;
+	int ret;
+
+	memset(&set_caching, 0, sizeof(set_caching));
+
+	set_caching.handle = bo_gem->gem_handle;
+	set_caching.cacheing = cache_mode;
+
+	ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_CACHEING, &set_caching);
+	if (ret == -1)
+		return -errno;
+
+	return 0;
+}
+
+static int
 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
 				     uint32_t tiling_mode,
 				     uint32_t stride)
-- 
1.8.1.5


-- 
Ville Syrjälä
Intel OTC