[Mesa-dev] [PATCH 2/3] i965/gen7: Set MOCS L3 cacheability for IVB/BYT

[Vedran Rodic]

On Tue, Sep 3, 2013 at 9:19 PM, Ville Syrjälä
<ville.syrjala at linux.intel.com> wrote:
> On Thu, Aug 15, 2013 at 10:39:31PM +0200, Vedran Rodic wrote:
>> > We do have the set_caching ioctl. It's enough to flip the PTEs to UC and
>> > let MOCS manage things. I actually did a few experiments on my IVB. I
>> > made all Mesa's buffers UC via PTEs by patching libdrm to change the
>> > cache mode of each bo after allocation. Then I fiddled with the MOCS
>> > LLC bits in various ways. It definitely has an effect, sometimes making
>> > things slower, sometimes faster. xonotic again seemed to benefit. IIRC
>> > leaving everything LLC uncached was actually the fastest (w/ high quality
>> > at least) so we may be thrashing the LLC a bit there. But eg. reaction
>> > quake regressed quite a lot if most things were left as UC.
>>
>> Can you share the libdrm patch?
>
> Sorry, forgot to reply.
>
> Here's the patch if you're still interested.

Thanks,

Just as a data point, I tried my OpenGL test application (Dota 2 on
Wine with my patches to enable fast depth clear), and performance
doesn't change when I use libdrm with your patch applied. I also
disabled all MOCS_L3 stuff for my IVB, still no changes.


Vedran