[Mesa-dev] [PATCH 2/2] radeonsi: pad IBs to a multiple of 8 DWs

[Alex Deucher]

Align IBs to 8 DW to align with the fetch
size of the CP.

Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
CC: "9.2" <mesa-stable at lists.freedesktop.org>
CC: "9.1" <mesa-stable at lists.freedesktop.org>
---
 src/gallium/drivers/radeonsi/r600_hw_context.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/r600_hw_context.c b/src/gallium/drivers/radeonsi/r600_hw_context.c
index 55daa82..fd86383 100644
--- a/src/gallium/drivers/radeonsi/r600_hw_context.c
+++ b/src/gallium/drivers/radeonsi/r600_hw_context.c
@@ -196,6 +196,7 @@ static void r600_flush_framebuffer(struct r600_context *ctx)
 void si_context_flush(struct r600_context *ctx, unsigned flags)
 {
 	struct radeon_winsys_cs *cs = ctx->cs;
+	unsigned i, padding_dw;
 	bool queries_suspended = false;
 
 #if 0
@@ -239,6 +240,20 @@ void si_context_flush(struct r600_context *ctx, unsigned flags)
 	}
 #endif
 
+	/* Pad the GFX CS to a multiple of 8 dwords to
+	 * align with CP fetch requirements.
+	 */
+	padding_dw = 8 - cs->cdw % 8;
+	if (padding_dw < 8) {
+		/* NOTE: type-2 packets are deprecated on CIK+ MEC (compute),
+		 * use type-3 instead.
+		 * PACKET3(PACKET3_NOP, 0x3FFF) for single DW type 3 NOP on CIK+
+		 */
+		for (i = 0; i < padding_dw; i++) {
+			cs->buf[cs->cdw++] = 0x80000000;
+		}
+	}
+
 	/* Flush the CS. */
 	ctx->ws->cs_flush(ctx->cs, flags, 0);
 
-- 
1.8.3.1