[Mesa-dev] [PATCH 2/2] radeonsi: pad IBs to a multiple of 8 DWs

[Michel Dänzer]

On Fre, 2013-09-06 at 10:36 -0400, Alex Deucher wrote:
> Align IBs to 8 DW to align with the fetch
> size of the CP.

[...]

> diff --git a/src/gallium/drivers/radeonsi/r600_hw_context.c b/src/gallium/drivers/radeonsi/r600_hw_context.c
> index 55daa82..fd86383 100644
> --- a/src/gallium/drivers/radeonsi/r600_hw_context.c
> +++ b/src/gallium/drivers/radeonsi/r600_hw_context.c

[...]

> @@ -239,6 +240,20 @@ void si_context_flush(struct r600_context *ctx, unsigned flags)
>  	}
>  #endif
>  
> +	/* Pad the GFX CS to a multiple of 8 dwords to
> +	 * align with CP fetch requirements.
> +	 */
> +	padding_dw = 8 - cs->cdw % 8;
> +	if (padding_dw < 8) {
> +		/* NOTE: type-2 packets are deprecated on CIK+ MEC (compute),
> +		 * use type-3 instead.
> +		 * PACKET3(PACKET3_NOP, 0x3FFF) for single DW type 3 NOP on CIK+
> +		 */

Could the code just do this, instead of having a comment?


> +		for (i = 0; i < padding_dw; i++) {
> +			cs->buf[cs->cdw++] = 0x80000000;
> +		}
> +	}

Any reason for this complicated logic, instead of simply:

	while (cs->cdw & 0x7)
		cs->buf[cs->cdw++] = 0x80000000;


Also, maybe this could be handled once in the winsys instead of
separately in each driver?


-- 
Earthling Michel Dänzer           |                   http://www.amd.com
Libre software enthusiast         |          Debian, X and DRI developer