[Mesa-dev] [PATCH] i965/hsw: compute DDX in a subspan based only on top row

[Chia-I Wu]

On Wed, Sep 18, 2013 at 6:27 AM, Mark Mueller <markkmueller at gmail.com> wrote:
> On Mon, Sep 16, 2013 at 1:31 AM, Chia-I Wu <olvaffe at gmail.com> wrote:
>>
>> On Mon, Sep 16, 2013 at 4:12 PM, Chia-I Wu <olvaffe at gmail.com> wrote:
>> > On Mon, Sep 16, 2013 at 3:50 AM, Mark Mueller <markkmueller at gmail.com>
>> > wrote:
>> >>
>> >>
>> >>
>> >> On Fri, Sep 13, 2013 at 2:15 PM, Paul Berry <stereotype441 at gmail.com>
>> >> wrote:
>> >>>
>> >>> On 12 September 2013 22:06, Chia-I Wu <olvaffe at gmail.com> wrote:
>> >>>>
>> >>>> From: Chia-I Wu <olv at lunarg.com>
>>
>> >>
>> >>
>> >> This scenario is where I'd place my bets, especially given that the
>> >> numbers
>> >> are based on Xonotic. I benchmarked this patch using Xonotic on Bay
>> >> Trail as
>> >> is and by replacing !brw->is_haswell with !brw->is_baytrail. With ultra
>> >> and
>> >> ultimate levels at medium and high resolutions, the results were all
>> >> essentially the same at comparable resolutions and quality levels.
>> > Isn't Bay Trail based on Ivy Bridge?
>> For Bay Trail, this might help you
>>
>>
>> http://lists.freedesktop.org/archives/mesa-dev/2013-September/044288.html
>>
>> if you are interested.
>
>
> Testing with Bay Trail shows no performance improvement with this patch.
> Most likely there are one or more CPU bottlenecks on Bay Tail that hide a
> majority of the performance gains of this change.
And no performance lost?  It could also be

 - the gain from SIMD16 was even out by the math ops
 - the lowering did not kick in because of one of the conditional checks
 - the game did not run in Ultra or Ultimate mode

I think the discussion belongs to that other thread.

>
>



-- 
olv at LunarG.com