[Mesa-dev] [PATCH 02/20] i965/blorp: Use program to offset W-tiled into correct level/layer
Topi Pohjolainen
topi.pohjolainen at intel.com
Fri Apr 11 00:28:42 PDT 2014
Once the logic is changed to treat the surface as linear one cannot
use the hardware for the layer/level shift anymore. Sampler engine
would try to base the calculation on linear layout which wouldn't
match the W-tiled. Similarly shifting the start address of the surface
wouldn't suffice as it could land anywhere within a W-tile.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 4 ++-
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 41 +++++++++++++++++++++++++---
2 files changed, 40 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 252219e..9cf5156 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -90,10 +90,12 @@ brw_blorp_surface_info::set(struct brw_context *brw,
case MESA_FORMAT_S_UINT8:
/* The miptree is a W-tiled stencil buffer. Surface states can't be set
* up for W tiling, so we'll need to use Y tiling and have the WM
- * program swizzle the coordinates.
+ * program swizzle the coordinates, and offset to correct level/layer.
*/
this->map_stencil_as_y_tiled = true;
this->brw_surfaceformat = BRW_SURFACEFORMAT_R8_UNORM;
+ this->width = mt->physical_width0;
+ this->height = mt->total_height;
break;
case MESA_FORMAT_Z24_UNORM_X8_UINT:
/* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index f1f58bf..66ad103 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1972,6 +1972,31 @@ compute_msaa_layout_for_pipeline(struct brw_context *brw, unsigned num_samples,
}
+/**
+ * Shift coordinates to the correct level/layer. Given offsets are real
+ * surface byte offsets while the coordinates to be adjusted are logical
+ * coordinates representing pixels. For single sampled surfaces these are the
+ * same thing but in multisampled case the offsets needs to be adjusted first
+ * according to the msaa configuration.
+ */
+static void
+shift_w_tiled_coords(float &x0, float &y0,
+ float &x1, float &y1,
+ unsigned num_samples,
+ unsigned x_offset, unsigned y_offset)
+{
+ if (num_samples) {
+ x_offset /= (num_samples / 2);
+ y_offset /= 2;
+ }
+
+ x0 += x_offset;
+ x1 += x_offset;
+ y0 += y_offset;
+ y1 += y_offset;
+}
+
+
brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
unsigned src_level, unsigned src_layer,
@@ -2129,6 +2154,14 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw,
wm_prog_key.src_layout = src_mt->msaa_layout;
wm_prog_key.dst_layout = dst_mt->msaa_layout;
+ /* Program offsets W-tiled surfaces internally to correct layer/level. */
+ if (src.map_stencil_as_y_tiled)
+ shift_w_tiled_coords(src_x0, src_y0, src_x1, src_y1,
+ src_mt->num_samples, src.x_offset, src.y_offset);
+ if (dst.map_stencil_as_y_tiled)
+ shift_w_tiled_coords(dst_x0, dst_y0, dst_x1, dst_y1,
+ src_mt->num_samples, dst.x_offset, dst.y_offset);
+
wm_prog_key.src_tiled_w = src.map_stencil_as_y_tiled;
wm_prog_key.dst_tiled_w = dst.map_stencil_as_y_tiled;
x0 = wm_push_consts.dst_x0 = dst_x0;
@@ -2231,8 +2264,8 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw,
y1 = ALIGN(y1, y_align) / 2;
dst.width = ALIGN(dst.width, x_align) * 2;
dst.height = ALIGN(dst.height, y_align) / 2;
- dst.x_offset *= 2;
- dst.y_offset /= 2;
+ dst.x_offset = 0;
+ dst.y_offset = 0;
wm_prog_key.use_kill = true;
}
@@ -2249,8 +2282,8 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw,
const unsigned x_align = 8, y_align = src.num_samples != 0 ? 8 : 4;
src.width = ALIGN(src.width, x_align) * 2;
src.height = ALIGN(src.height, y_align) / 2;
- src.x_offset *= 2;
- src.y_offset /= 2;
+ src.x_offset = 0;
+ src.y_offset = 0;
}
}
--
1.8.3.1
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