[Mesa-dev] [PATCH 03/20] i965/blorp: Drop unnecessary tile offset calculator
Topi Pohjolainen
topi.pohjolainen at intel.com
Fri Apr 11 00:28:43 PDT 2014
Now that blorp program offsets w-tiled internally, the surface setup
support is not needed anymore.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 26 --------------------------
src/mesa/drivers/dri/i965/brw_blorp.h | 2 --
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 4 ----
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 10 +++++++---
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 11 +++++++----
5 files changed, 14 insertions(+), 39 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 9cf5156..82e30d4 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -130,32 +130,6 @@ brw_blorp_surface_info::set(struct brw_context *brw,
}
-/**
- * Split x_offset and y_offset into a base offset (in bytes) and a remaining
- * x/y offset (in pixels). Note: we can't do this by calling
- * intel_renderbuffer_tile_offsets(), because the offsets may have been
- * adjusted to account for Y vs. W tiling differences. So we compute it
- * directly from the adjusted offsets.
- */
-uint32_t
-brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
- uint32_t *tile_y) const
-{
- struct intel_region *region = mt->region;
- uint32_t mask_x, mask_y;
-
- intel_region_get_tile_masks(region, &mask_x, &mask_y,
- map_stencil_as_y_tiled);
-
- *tile_x = x_offset & mask_x;
- *tile_y = y_offset & mask_y;
-
- return intel_region_get_aligned_offset(region, x_offset & ~mask_x,
- y_offset & ~mask_y,
- map_stencil_as_y_tiled);
-}
-
-
brw_blorp_params::brw_blorp_params()
: x0(0),
y0(0),
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index db41497..ba7f42d 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -130,8 +130,6 @@ public:
unsigned int level, unsigned int layer,
bool is_render_target);
- uint32_t compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const;
-
/* Setting this flag indicates that the buffer's contents are W-tiled
* stencil data, but the surface state should be set up for Y tiled
* MESA_FORMAT_R_UNORM8 data (this is necessary because surface states don't
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 66ad103..4fc3b7c 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -2264,8 +2264,6 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw,
y1 = ALIGN(y1, y_align) / 2;
dst.width = ALIGN(dst.width, x_align) * 2;
dst.height = ALIGN(dst.height, y_align) / 2;
- dst.x_offset = 0;
- dst.y_offset = 0;
wm_prog_key.use_kill = true;
}
@@ -2282,8 +2280,6 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw,
const unsigned x_align = 8, y_align = src.num_samples != 0 ? 8 : 4;
src.width = ALIGN(src.width, x_align) * 2;
src.height = ALIGN(src.height, y_align) / 2;
- src.x_offset = 0;
- src.y_offset = 0;
}
}
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 5f38857..4b6430b 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -368,7 +368,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
height /= 2;
}
struct intel_region *region = surface->mt->region;
- uint32_t tile_x, tile_y;
+ uint32_t tile_x = 0, tile_y = 0;
uint32_t *surf = (uint32_t *)
brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
@@ -380,8 +380,12 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT);
/* reloc */
- surf[1] = (surface->compute_tile_offsets(&tile_x, &tile_y) +
- region->bo->offset64);
+ surf[1] = region->bo->offset64;
+ if (!surface->map_stencil_as_y_tiled)
+ surf[1] += intel_miptree_get_tile_offsets(surface->mt,
+ surface->level,
+ surface->layer,
+ &tile_x, &tile_y);
surf[2] = (0 << BRW_SURFACE_LOD_SHIFT |
(width - 1) << BRW_SURFACE_WIDTH_SHIFT |
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 3a89d34..ab76bee 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -150,7 +150,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
* gen6_blorp_emit_surface_state).
*/
struct intel_region *region = surface->mt->region;
- uint32_t tile_x, tile_y;
+ uint32_t tile_x = 0, tile_y = 0;
const uint8_t mocs = GEN7_MOCS_L3;
uint32_t tiling = surface->map_stencil_as_y_tiled
@@ -174,9 +174,12 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
else
surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
- /* reloc */
- surf[1] =
- surface->compute_tile_offsets(&tile_x, &tile_y) + region->bo->offset64;
+ surf[1] = region->bo->offset64;
+ if (!surface->map_stencil_as_y_tiled)
+ surf[1] += intel_miptree_get_tile_offsets(surface->mt,
+ surface->level,
+ surface->layer,
+ &tile_x, &tile_y);
/* Note that the low bits of these fields are missing, so
* there's the possibility of getting in trouble.
--
1.8.3.1
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