[Mesa-dev] [PATCH v2 09/13] i965/fs: don't pass in ir_texture to emit_texture_*
Connor Abbott
cwabbott0 at gmail.com
Mon Aug 4 15:20:46 PDT 2014
At this point, the only thing it's used for is the opcode.
Signed-off-by: Connor Abbott <connor.abbott at intel.com>
---
src/mesa/drivers/dri/i965/brw_fs.h | 27 ++++++++------
src/mesa/drivers/dri/i965/brw_fs_fp.cpp | 6 +--
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 55 +++++++++++++++-------------
3 files changed, 47 insertions(+), 41 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 756d569..b86e65e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -372,18 +372,21 @@ public:
void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
fs_reg rescale_texcoord(fs_reg coordinate, const glsl_type *coord_type,
bool is_rect, int sampler, int texunit);
- fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- int coord_components, fs_reg shadow_comp,
- fs_reg lod, fs_reg lod2, int lod_components);
- fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- int coord_components, fs_reg shadow_comp,
- fs_reg lod, fs_reg lod2, int lod_components,
- fs_reg sample_index, bool has_offset);
- fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- int coord_components, fs_reg shadow_comp,
- fs_reg lod, fs_reg lod2, int lod_components,
- fs_reg sample_index, bool has_offset,
- fs_reg offset, fs_reg mcs, int sampler);
+ fs_inst *emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
+ fs_reg coordinate, int coord_components,
+ fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
+ int lod_components);
+ fs_inst *emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
+ fs_reg coordinate, int coord_components,
+ fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
+ int lod_components, fs_reg sample_index,
+ bool has_offset);
+ fs_inst *emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
+ fs_reg coordinate, int coord_components,
+ fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
+ int lod_components, fs_reg sample_index,
+ bool has_offset, fs_reg offset, fs_reg mcs,
+ int sampler);
fs_reg emit_mcs_fetch(fs_reg coordinate, int components, int sampler);
void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
fs_reg fix_math_operand(fs_reg src);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
index 639d8a8..7048ed4 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
@@ -489,11 +489,11 @@ fs_visitor::emit_fragment_program_code()
fs_inst *inst;
if (brw->gen >= 7) {
- inst = emit_texture_gen7(ir, dst, coordinate, coord_components, shadow_c, lod, dpdy, 0, sample_index, false, offset_reg, fs_reg(0u), fpi->TexSrcUnit);
+ inst = emit_texture_gen7(ir->op, dst, coordinate, coord_components, shadow_c, lod, dpdy, 0, sample_index, false, offset_reg, fs_reg(0u), fpi->TexSrcUnit);
} else if (brw->gen >= 5) {
- inst = emit_texture_gen5(ir, dst, coordinate, coord_components, shadow_c, lod, dpdy, 0, sample_index, false);
+ inst = emit_texture_gen5(ir->op, dst, coordinate, coord_components, shadow_c, lod, dpdy, 0, sample_index, false);
} else {
- inst = emit_texture_gen4(ir, dst, coordinate, coord_components, shadow_c, lod, dpdy, 0);
+ inst = emit_texture_gen4(ir->op, dst, coordinate, coord_components, shadow_c, lod, dpdy, 0);
}
inst->sampler = fpi->TexSrcUnit;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index cba6182..3ac19c1 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1094,9 +1094,10 @@ fs_visitor::visit(ir_assignment *ir)
}
fs_inst *
-fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- int coord_components, fs_reg shadow_c,
- fs_reg lod, fs_reg dPdy, int lod_components)
+fs_visitor::emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
+ fs_reg coordinate, int coord_components,
+ fs_reg shadow_c, fs_reg lod, fs_reg dPdy,
+ int lod_components)
{
int mlen;
int base_mrf = 1;
@@ -1120,13 +1121,13 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
}
mlen += 3;
- if (ir->op == ir_tex) {
+ if (op == ir_tex) {
/* There's no plain shadow compare message, so we use shadow
* compare with a bias of 0.0.
*/
emit(MOV(fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)));
mlen++;
- } else if (ir->op == ir_txb || ir->op == ir_txl) {
+ } else if (op == ir_txb || op == ir_txl) {
emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
mlen++;
} else {
@@ -1135,7 +1136,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
mlen++;
- } else if (ir->op == ir_tex) {
+ } else if (op == ir_tex) {
for (int i = 0; i < coord_components; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
coordinate.reg_offset++;
@@ -1146,7 +1147,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
}
/* gen4's SIMD8 sampler always has the slots for u,v,r present. */
mlen += 3;
- } else if (ir->op == ir_txd) {
+ } else if (op == ir_txd) {
fs_reg &dPdx = lod;
for (int i = 0; i < coord_components; i++) {
@@ -1181,7 +1182,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
dPdy.reg_offset++;
}
mlen += MAX2(lod_components, 2);
- } else if (ir->op == ir_txs) {
+ } else if (op == ir_txs) {
/* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
simd16 = true;
emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
@@ -1191,7 +1192,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
* instructions. We'll need to do SIMD16 here.
*/
simd16 = true;
- assert(ir->op == ir_txb || ir->op == ir_txl || ir->op == ir_txf);
+ assert(op == ir_txb || op == ir_txl || op == ir_txf);
for (int i = 0; i < coord_components; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen + i * 2, coordinate.type),
@@ -1226,7 +1227,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
}
fs_inst *inst = NULL;
- switch (ir->op) {
+ switch (op) {
case ir_tex:
inst = emit(SHADER_OPCODE_TEX, dst, reg_undef);
break;
@@ -1273,10 +1274,11 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
* surprising in the disassembly.
*/
fs_inst *
-fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- int coord_components, fs_reg shadow_c,
- fs_reg lod, fs_reg lod2, int lod_components,
- fs_reg sample_index, bool has_offset)
+fs_visitor::emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
+ fs_reg coordinate, int coord_components,
+ fs_reg shadow_c, fs_reg lod, fs_reg lod2,
+ int lod_components, fs_reg sample_index,
+ bool has_offset)
{
int mlen = 0;
int base_mrf = 2;
@@ -1307,7 +1309,7 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
}
fs_inst *inst = NULL;
- switch (ir->op) {
+ switch (op) {
case ir_tex:
inst = emit(SHADER_OPCODE_TEX, dst, reg_undef);
break;
@@ -1399,11 +1401,12 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
}
fs_inst *
-fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- int coord_components, fs_reg shadow_c,
- fs_reg lod, fs_reg lod2, int lod_components,
- fs_reg sample_index, bool has_offset,
- fs_reg offset, fs_reg mcs, int sampler)
+fs_visitor::emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
+ fs_reg coordinate, int coord_components,
+ fs_reg shadow_c, fs_reg lod, fs_reg lod2,
+ int lod_components, fs_reg sample_index,
+ bool has_offset, fs_reg offset, fs_reg mcs,
+ int sampler)
{
int reg_width = dispatch_width / 8;
bool header_present = false;
@@ -1414,7 +1417,7 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
}
int length = 0;
- if (ir->op == ir_tg4 || (has_offset && ir->op != ir_txf) || sampler >= 16) {
+ if (op == ir_tg4 || (has_offset && op != ir_txf) || sampler >= 16) {
/* For general texture offsets (no txf workaround), we need a header to
* put them in. Note that for SIMD16 we're making space for two actual
* hardware registers here, so the emit will have to fix up for this.
@@ -1439,7 +1442,7 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
bool coordinate_done = false;
/* Set up the LOD info */
- switch (ir->op) {
+ switch (op) {
case ir_tex:
case ir_lod:
break;
@@ -1567,7 +1570,7 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
/* Generate the SEND */
enum opcode opcode;
- switch (ir->op) {
+ switch (op) {
case ir_tex: opcode = SHADER_OPCODE_TEX; break;
case ir_txb: opcode = FS_OPCODE_TXB; break;
case ir_txl: opcode = SHADER_OPCODE_TXL; break;
@@ -1864,15 +1867,15 @@ fs_visitor::visit(ir_texture *ir)
}
if (brw->gen >= 7) {
- inst = emit_texture_gen7(ir, dst, coordinate, coord_components,
+ inst = emit_texture_gen7(ir->op, dst, coordinate, coord_components,
shadow_comparitor, lod, lod2, lod_components,
sample_index, has_offset, offset, mcs, sampler);
} else if (brw->gen >= 5) {
- inst = emit_texture_gen5(ir, dst, coordinate, coord_components,
+ inst = emit_texture_gen5(ir->op, dst, coordinate, coord_components,
shadow_comparitor, lod, lod2, lod_components,
sample_index, has_offset);
} else {
- inst = emit_texture_gen4(ir, dst, coordinate, coord_components,
+ inst = emit_texture_gen4(ir->op, dst, coordinate, coord_components,
shadow_comparitor, lod, lod2, lod_components);
}
--
1.9.3
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