[Mesa-dev] [PATCH] i965/gen4-5: Cope with immutable-format texture revalidation

[Kenneth Graunke]

On Monday, December 08, 2014 08:37:00 PM Chris Forbes wrote:
> This is unfortunately sometimes necessary due to rebasing levels when
> rendering into them.
> 
> 16 piglits crash -> pass, when building mesa with debug enabled.
> 
> Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
> ---
>  src/mesa/drivers/dri/i965/intel_tex_validate.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c
> index 0bf0393..1d82768 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
> +++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
> @@ -98,10 +98,17 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit)
>        return true;
>     }
>  
> -   /* Immutable textures should not get this far -- they should have been
> -    * created in a validated state, and nothing can invalidate them.
> +   /* On recent generations, immutable textures should not get this far
> +    * -- they should have been created in a validated state, and nothing
> +    * can invalidate them.
> +    *
> +    * Unfortunately, this is not true on pre-Sandybridge hardware -- when
> +    * rendering into an immutable-format depth texture we may have to rebase
> +    * the rendered levels to meet alignment requirements.
> +    *
> +    * FINISHME: Avoid doing this.
>      */
> -   assert(!tObj->Immutable);
> +   assert(!tObj->Immutable || brw->gen < 6);
>  
>     firstImage = intel_texture_image(tObj->Image[0][tObj->BaseLevel]);

I originally thought of the tile_x/tile_y restriction, which is only the case
on Broadwater/Crestline (gen4.0), but apparently we do this for depth/stencil
misalignment as well.

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

We can probably adopt the same approach used by SNB on ILK at least, and maybe
G45...which would avoid the need for this.

It's probably unavoidable on original Gen4.

--Ken
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