[Mesa-dev] [PATCH 1/4] i965/byt: Allow 128 bpp to be linear or Y-tiled on

[Ben Widawsky]

Let's assume that this IVB specific feature exists on BYT too, since it's very
much like IVB

Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 7081f1d..4ae700c 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -490,7 +490,7 @@ intel_miptree_choose_tiling(struct brw_context *brw,
     * 128 bits per pixel translates to 16 bytes per pixel.  This is necessary
     * all the way back to 965, but is explicitly permitted on Gen7.
     */
-   if (brw->gen != 7 && mt->cpp >= 16)
+   if ((brw->gen != 7 && !brw->is_baytrail) && mt->cpp >= 16)
       return I915_TILING_X;
 
    /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
-- 
2.1.3