[Mesa-dev] [PATCH 2/4] i965: Allow other tiling formats for 128 bpp on gen6+

[Ben Widawsky]

The most recent docs I can find say this workaround is needed for Sandybridge
only. It says GEN6+ support linear, X, and Y, while GEN6 must be X or Y.

commit c189840b21e176d87cbb382e64e848061b8c7b06
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Tue Aug 13 15:03:12 2013 -0700

    i965: Force X-tiling for 128 bpp formats on Sandybridge.

The above commit has a mailing list discussion about this where Ken said the
issue was reintroduced on later GENs. I can't find the evidence to support this
anymore, so let's turn it on and hope for the best.

Cc: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 4ae700c..efe63b5 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -490,7 +490,7 @@ intel_miptree_choose_tiling(struct brw_context *brw,
     * 128 bits per pixel translates to 16 bytes per pixel.  This is necessary
     * all the way back to 965, but is explicitly permitted on Gen7.
     */
-   if ((brw->gen != 7 && !brw->is_baytrail) && mt->cpp >= 16)
+   if (brw->gen <= 6)
       return I915_TILING_X;
 
    /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
-- 
2.1.3