[Mesa-dev] [PATCH 2/8] i965: Micro-optimize brw_get_index_type

[Kenneth Graunke]

On Friday, December 19, 2014 02:20:53 PM Ian Romanick wrote:
[snip]
> diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
> index a63c483..92eb022 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.h
> +++ b/src/mesa/drivers/dri/i965/brw_context.h
> @@ -1602,7 +1602,27 @@ gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx);
>  /* brw_draw_upload.c */
>  unsigned brw_get_vertex_surface_type(struct brw_context *brw,
>                                       const struct gl_client_array *glarray);
> -unsigned brw_get_index_type(GLenum type);
> +
> +static inline unsigned
> +brw_get_index_type(GLenum type)
> +{
> +   assert((type == GL_UNSIGNED_BYTE)
> +          || (type == GL_UNSIGNED_SHORT)
> +          || (type == GL_UNSIGNED_INT));
> +
> +   /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
> +    * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
> +    * to map to scale factors of 0, 1, and 2, respectively.  These scale
> +    * factors are then left-shfited by 8 to be in the correct position in the
> +    * CMD_INDEX_BUFFER packet.
> +    *
> +    * Subtracting 0x1401 gives 0, 2, and 4.  Shifting left by 7 afterwards
> +    * gives 0x00000000, 0x00000100, and 0x00000200.  These just happen to be
> +    * the values the need to be written in the CMD_INDEX_BUFFER packet.
> +    */
> +   return (type - 0x1401) << 7;
> +}

Clever!

How about putting it in brw_draw.h?  It seems like the right place, and would
avoid cluttering brw_context.h with even more random stuff.

With Matt's suggestions, this is:
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

I don't care about removing the BRW_INDEX_* #defines - either way's fine.
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