[Mesa-dev] [PATCH 3/3] d3d10: support 1d indirect addressing on inputs
Zack Rusin
zackr at vmware.com
Tue Feb 4 03:52:52 CET 2014
we supported 2d indirect addressing (gs tests were using it) but
not 1d indirect addressing (which can be used in vs and ps). This
adds support for 1d indirect addressing.
Signed-off-by: Zack Rusin <zackr at vmware.com>
---
src/gallium/state_trackers/d3d10/ShaderTGSI.c | 26 ++++++++++++++++++++++----
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/src/gallium/state_trackers/d3d10/ShaderTGSI.c b/src/gallium/state_trackers/d3d10/ShaderTGSI.c
index 1cf9e0e..76126c5 100644
--- a/src/gallium/state_trackers/d3d10/ShaderTGSI.c
+++ b/src/gallium/state_trackers/d3d10/ShaderTGSI.c
@@ -828,11 +828,29 @@ translate_src_operand(struct Shader_xlate *sx,
switch (operand->base.type) {
case D3D10_SB_OPERAND_TYPE_INPUT:
if (operand->base.index_dim == 1) {
- assert(operand->base.index[0].index_rep ==
- D3D10_SB_OPERAND_INDEX_IMMEDIATE32);
- assert(operand->base.index[0].imm < SHADER_MAX_INPUTS);
+ switch (operand->base.index[0].index_rep) {
+ case D3D10_SB_OPERAND_INDEX_IMMEDIATE32:
+ assert(operand->base.index[0].imm < SHADER_MAX_INPUTS);
+ reg = sx->inputs[operand->base.index[0].imm].reg;
+ break;
+ case D3D10_SB_OPERAND_INDEX_RELATIVE: {
+ struct ureg_src tmp =
+ translate_relative_operand(sx, &operand->base.index[0].rel);
+ reg = ureg_src_indirect(sx->inputs[0].reg, tmp);
+ }
+ break;
+ case D3D10_SB_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE: {
+ struct ureg_src tmp =
+ translate_relative_operand(sx, &operand->base.index[0].rel);
+ reg = ureg_src_indirect(sx->inputs[operand->base.index[0].imm].reg, tmp);
+ }
+ break;
+ default:
+ /* XXX: Other index representations.
+ */
+ LOG_UNSUPPORTED(TRUE);
- reg = sx->inputs[operand->base.index[0].imm].reg;
+ }
} else {
assert(operand->base.index_dim == 2);
assert(operand->base.index[1].imm < SHADER_MAX_INPUTS);
--
1.8.3.2
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