[Mesa-dev] [PATCH 2/7] i965/blorp: split calculations of page and tile offsets

[Topi Pohjolainen]

These will be handled separately in the coming patches.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_blorp.cpp  | 21 +++++++++++++++++----
 src/mesa/drivers/dri/i965/brw_blorp.h    |  3 ++-
 src/mesa/drivers/dri/i965/gen6_blorp.cpp |  4 ++--
 src/mesa/drivers/dri/i965/gen7_blorp.cpp |  4 ++--
 4 files changed, 23 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 7bdf83a..6fc215f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -135,14 +135,13 @@ brw_blorp_surface_info::set(struct brw_context *brw,
  * adjusted to account for Y vs. W tiling differences.  So we compute it
  * directly from the adjusted offsets.
  */
-uint32_t
+void
 brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
                                              uint32_t *tile_y) const
 {
-   struct intel_region *region = mt->region;
    uint32_t mask_x, mask_y;
 
-   intel_region_get_tile_masks(region, &mask_x, &mask_y,
+   intel_region_get_tile_masks(mt->region, &mask_x, &mask_y,
                                map_stencil_as_y_tiled);
 
    *tile_x = x_offset & mask_x;
@@ -153,8 +152,22 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
     */
    assert(*tile_x % 4 == 0);
    assert(*tile_y % 2 == 0);
+}
+
+
+/**
+ * Resolve the page aligned offset from the base address excluding the
+ * remaining part within the tile.
+ */
+uint32_t
+brw_blorp_surface_info::compute_page_offset() const
+{
+   uint32_t mask_x, mask_y;
+
+   intel_region_get_tile_masks(mt->region, &mask_x, &mask_y,
+                               map_stencil_as_y_tiled);
 
-   return intel_region_get_aligned_offset(region, x_offset & ~mask_x,
+   return intel_region_get_aligned_offset(mt->region, x_offset & ~mask_x,
                                           y_offset & ~mask_y,
                                           map_stencil_as_y_tiled);
 }
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index db41497..bbd6481 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -130,7 +130,8 @@ public:
             unsigned int level, unsigned int layer,
             bool is_render_target);
 
-   uint32_t compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const;
+   uint32_t compute_page_offset() const;
+   void compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const;
 
    /* Setting this flag indicates that the buffer's contents are W-tiled
     * stencil data, but the surface state should be set up for Y tiled
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 8d45d57..75900b8 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -380,8 +380,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
               surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT);
 
    /* reloc */
-   surf[1] = (surface->compute_tile_offsets(&tile_x, &tile_y) +
-              region->bo->offset64);
+   surf[1] = surface->compute_page_offset() + region->bo->offset64;
 
    surf[2] = (0 << BRW_SURFACE_LOD_SHIFT |
               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
@@ -399,6 +398,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
 
    surf[4] = brw_get_surface_num_multisamples(surface->num_samples);
 
+   surface->compute_tile_offsets(&tile_x, &tile_y);
    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
               (surface->mt->align_h == 4 ?
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index f067b0b..f6afab2 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -175,9 +175,9 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
       surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
 
    /* reloc */
-   surf[1] =
-      surface->compute_tile_offsets(&tile_x, &tile_y) + region->bo->offset64;
+   surf[1] = surface->compute_page_offset() + region->bo->offset64;
 
+   surface->compute_tile_offsets(&tile_x, &tile_y);
    surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
              SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET) |
              SET_FIELD(mocs, GEN7_SURFACE_MOCS);
-- 
1.8.3.1