[Mesa-dev] [PATCH 3/7] i965/blorp: add intra-tile offset support without surface config
Topi Pohjolainen
topi.pohjolainen at intel.com
Mon Feb 10 11:53:11 PST 2014
In gen6/7 the surface state can be adjusted with these directly but
starting from gen8 there isn't that option anymore.
In this patch these are still just zero and have no effect.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 42 +++++++++++++++++++++++++++-
src/mesa/drivers/dri/i965/brw_blorp.h | 18 ++++++++++++
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 5 ++++
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 24 ++++++++++++----
4 files changed, 83 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 6fc215f..0b749a9 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -46,7 +46,9 @@ brw_blorp_mip_info::brw_blorp_mip_info()
brw_blorp_surface_info::brw_blorp_surface_info()
: map_stencil_as_y_tiled(false),
- num_samples(0)
+ num_samples(0),
+ tile_x(0),
+ tile_y(0)
{
}
@@ -173,6 +175,44 @@ brw_blorp_surface_info::compute_page_offset() const
}
+/**
+ * Setup surface offsets needed for a shift from the base address of the
+ * surface to the beginning of the miplevel of interest. Destination offsets
+ * are configured for the pipeline (vertices, drawing rectangle) and their
+ * effect needs to be compensated when considering sampling coordinates for
+ * the source.
+ * It should be noted that there is need for the same offsets in two different
+ * spaces. In native X and Y-tiling cases these offsets are equal but when
+ * originally W-tiled surfaces are pretended to be Y-tiled the offsets given
+ * for the surface configuration differ from the ones used within the blorp
+ * program itself.
+ */
+void
+brw_blorp_params::configure_miplevel_offsets()
+{
+ uint32_t src_tile_orig_space_x = 0;
+ uint32_t src_tile_orig_space_y = 0;
+ uint32_t dst_tile_orig_space_x = 0;
+ uint32_t dst_tile_orig_space_y = 0;
+
+ /* Compensate for the adjusted destination offsets when calculating the
+ * corresponding sampling coordinates for the source.
+ */
+ wm_push_consts.x_transform.offset -= dst_tile_orig_space_x;
+ wm_push_consts.y_transform.offset -= dst_tile_orig_space_y;
+
+ /* Shift the source itself according to its offsets. */
+ wm_push_consts.x_transform.offset += src_tile_orig_space_x;
+ wm_push_consts.y_transform.offset += src_tile_orig_space_y;
+
+ /* Also adjust the destination clipping rectangle (pixel killing). */
+ wm_push_consts.dst_x0 += dst_tile_orig_space_x;
+ wm_push_consts.dst_x1 += dst_tile_orig_space_x;
+ wm_push_consts.dst_y0 += dst_tile_orig_space_y;
+ wm_push_consts.dst_y1 += dst_tile_orig_space_y;
+}
+
+
brw_blorp_params::brw_blorp_params()
: x0(0),
y0(0),
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index bbd6481..0820e9d 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -166,6 +166,23 @@ public:
* surface state for this surface.
*/
intel_msaa_layout msaa_layout;
+
+ /* Offsets within tile indicating the beginning of the mipmap level. The
+ * buffer object base address can be adjusted in the surface state taking
+ * into account full tiles (pages) but the remaining offset within the
+ * page needs to be handled separately.
+ * Offset in the destination is taken into account when setting up the
+ * vertices for the pipeline. It is also considered within the shader
+ * when resolving the sampling coordinates for the source surface and
+ * setting up the clipping boundaries for the destination itself.
+ * Source offset in turn is handled fully in the shader as part of the
+ * sampling coordinate calculation.
+ * Both source and destination offsets are also used in the surface state
+ * setup phase to adjust the surface dimensions allowing for the shift in
+ * the beginning of the read/write.
+ */
+ uint32_t tile_x;
+ uint32_t tile_y;
};
@@ -224,6 +241,7 @@ public:
virtual uint32_t get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data) const = 0;
+ void configure_miplevel_offsets();
uint32_t x0;
uint32_t y0;
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index c23504f..c5456a0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -2242,6 +2242,11 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw,
src.x_offset *= 2;
src.y_offset /= 2;
}
+
+ /* Now that possible compensation for W-tiling is done it is possible to
+ * calculate any offsets needed for accessing miplevels other than zero.
+ */
+ configure_miplevel_offsets();
}
uint32_t
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 75900b8..8f257a7 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -128,14 +128,24 @@ gen6_blorp_emit_vertices(struct brw_context *brw,
*
* For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
* "Vertex URB Entry (VUE) Formats".
+ *
+ * Coordinates are adjusted to take into account possible offset from the
+ * beginnning of the surface to the beginning of a mip-level other than
+ * zero. The offset is divided into two parts: full pages (tiles) and
+ * offset within a tile. Former is taken cared of in the surface state
+ * setup while the latter is considered here.
*/
{
float *vertex_data;
+ const float x0 = (float)(params->x0 + params->dst.tile_x);
+ const float x1 = (float)(params->x1 + params->dst.tile_x);
+ const float y0 = (float)(params->y0 + params->dst.tile_y);
+ const float y1 = (float)(params->y1 + params->dst.tile_y);
const float vertices[GEN6_BLORP_VBO_SIZE] = {
- /* v0 */ 0, 0, 0, 0, (float) params->x0, (float) params->y1, 0, 1,
- /* v1 */ 0, 0, 0, 0, (float) params->x1, (float) params->y1, 0, 1,
- /* v2 */ 0, 0, 0, 0, (float) params->x0, (float) params->y0, 0, 1,
+ /* v0 */ 0, 0, 0, 0, x0, y1, 0, 1,
+ /* v1 */ 0, 0, 0, 0, x1, y1, 0, 1,
+ /* v2 */ 0, 0, 0, 0, x0, y0, 0, 1,
};
vertex_data = (float *) brw_state_batch(brw, AUB_TRACE_VERTEX_BUFFER,
@@ -939,8 +949,12 @@ gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
OUT_BATCH(0);
- OUT_BATCH(((params->x1 - 1) & 0xffff) |
- ((params->y1 - 1) << 16));
+ /* Adjust the rectangle to allow for the shift in mip-level origin. Full
+ * tiles are taken into account in surface state setup. This compensates
+ * for the remaining offset within a tile.
+ */
+ OUT_BATCH((((params->x1 + params->dst.tile_x) - 1) & 0xffff) |
+ (((params->y1 + params->dst.tile_y) - 1) << 16));
OUT_BATCH(0);
ADVANCE_BATCH();
}
--
1.8.3.1
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