[Mesa-dev] [PATCH 22/25] i965/gen6+: Factor out PIPE_CONTROL submission from intel_batchbuffer_emit_mi_flush.

[Paul Berry]

On 2 December 2013 11:42, Francisco Jerez <currojerez at riseup.net> wrote:

> ---
>  src/mesa/drivers/dri/i965/intel_batchbuffer.c | 54
> ++++++++++++++++-----------
>  src/mesa/drivers/dri/i965/intel_batchbuffer.h |  2 +
>  2 files changed, 34 insertions(+), 22 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> index 25aacd9..d11de49 100644
> --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> @@ -633,6 +633,30 @@ intel_emit_post_sync_nonzero_flush(struct brw_context
> *brw)
>     brw->batch.need_workaround_flush = false;
>  }
>
> +void
> +intel_batchbuffer_emit_pipe_control(struct brw_context *brw,
> +                                    unsigned bits)
> +{
> +   assert(brw->gen >= 6);
>

Since this function is gen6+ only, but there exist pipe controls on
previous generations, can we call it something like
gen6_batchbuffer_emit_pipe_control()?

With that change, the patch is:

Reviewed-by: Paul Berry <stereotype441 at gmail.com>
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