[Mesa-dev] [RFC PATCH 14/16] i965/gen6: Stencil/hiz needs an offset for LOD > 0

[Jordan Justen]

On Mon, Jun 2, 2014 at 3:00 AM, Pohjolainen, Topi
<topi.pohjolainen at intel.com> wrote:
> On Thu, May 29, 2014 at 01:53:53PM -0700, Jordan Justen wrote:
>> Since gen6 stencil only supports LOD0, we need to program an offset to
>> the LOD when emitting the stencil/hiz.
>>
>> Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
>> ---
>>  src/mesa/drivers/dri/i965/gen6_blorp.cpp     | 10 ++++++++-
>>  src/mesa/drivers/dri/i965/gen6_depth_state.c | 32 ++++++++++++++++++++++++++--
>>  2 files changed, 39 insertions(+), 3 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
>> index 7be8ccd..920f435 100644
>> --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
>> +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
>> @@ -872,13 +872,21 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
>>     /* 3DSTATE_HIER_DEPTH_BUFFER */
>>     {
>>        struct intel_mipmap_tree *hiz_mt = params->depth.mt->hiz_mt;
>> +      uint32_t offset = 0;
>> +
>> +      if (hiz_mt->array_spacing_lod0) {
>> +         offset = intel_miptree_get_aligned_offset(hiz_mt,
>> +                                                   hiz_mt->level[lod].level_x,
>> +                                                   hiz_mt->level[lod].level_y,
>
> These lines are longer than 80 columns.
>
>> +                                                   false);
>> +      }
>>
>>        BEGIN_BATCH(3);
>>        OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
>>        OUT_BATCH(hiz_mt->pitch - 1);
>>        OUT_RELOC(hiz_mt->bo,
>>                  I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
>> -                0);
>> +                offset);
>>        ADVANCE_BATCH();
>>     }
>>
>> diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
>> index 3ef2fab..8fcc0a8 100644
>> --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
>> +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
>> @@ -271,12 +271,21 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
>>        /* Emit hiz buffer. */
>>        if (hiz) {
>>           struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
>> +         uint32_t offset = 0;
>> +
>> +         if (hiz_mt->array_spacing_lod0) {
>> +            offset = intel_miptree_get_aligned_offset(hiz_mt,
>> +                                                      hiz_mt->level[lod].level_x,
>> +                                                      hiz_mt->level[lod].level_y,
>
> Same here.
>
>> +                                                      false);
>> +         }
>> +
>>        BEGIN_BATCH(3);
>>        OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
>>        OUT_BATCH(hiz_mt->pitch - 1);
>>        OUT_RELOC(hiz_mt->bo,
>>                  I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
>> -                0);
>> +                offset);
>>        ADVANCE_BATCH();
>>        } else {
>>        BEGIN_BATCH(3);
>> @@ -288,6 +297,25 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
>>
>>        /* Emit stencil buffer. */
>>        if (separate_stencil) {
>> +         uint32_t offset = 0;
>> +
>> +         if (stencil_mt->array_spacing_lod0) {
>> +            if (stencil_mt->format == MESA_FORMAT_S_UINT8) {
>> +               /* Note: we can't compute the stencil offset using
>> +                * intel_region_get_aligned_offset(), because stencil_region claims
>
> This line is longer than 80 columns.
>
>> +                * that the region is untiled even though it's W tiled.
>> +                */
>> +               offset =
>> +                  stencil_mt->level[lod].level_y * stencil_mt->pitch +
>> +                  stencil_mt->level[lod].level_x * 64;
>
> Why is the x-coordinate multiplied? And I don't think the result is aligned
> to tile boundary.

Hmm, I got this from brw_misc_state.c.

So far, stencil breaks if I try anything other than this code. :(

-Jordan

>> +            } else {
>> +               offset = intel_miptree_get_aligned_offset(stencil_mt,
>> +                                                         stencil_mt->level[lod].level_x,
>> +                                                         stencil_mt->level[lod].level_y,
>
> These lines are also longer than 80 columns.
>
>> +                                                         false);
>> +            }
>> +         }
>> +
>>        BEGIN_BATCH(3);
>>        OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
>>           /* The stencil buffer has quirky pitch requirements.  From Vol 2a,
>> @@ -298,7 +326,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
>>        OUT_BATCH(2 * stencil_mt->pitch - 1);
>>        OUT_RELOC(stencil_mt->bo,
>>                  I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
>> -                0);
>> +                offset);
>>        ADVANCE_BATCH();
>>        } else {
>>        BEGIN_BATCH(3);
>> --
>> 2.0.0.rc4
>>
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