[Mesa-dev] [PATCH 17/17] i965/gen6: Force non_mip_arrays for separate stencil/hiz

[Pohjolainen, Topi]

On Fri, Jul 18, 2014 at 02:16:52PM -0700, Jordan Justen wrote:
> For gen6 we will use non-mipmapped array spacing, but with multiple
> mip levels. This is needed because gen6 hiz and separate stencil only
> support a single mip-level.
> 
> PRM Volume 1, Part 1, 7.18.3.7.2 For separate stencil buffer [DevILK]
> to [DevSNB]:
>  "The separate stencil buffer does not support mip mapping, thus the
>   storage for LODs other than LOD 0 is not needed."
> 
> We still allocate storage for the other stencil mip-levels within a
> single texture, but each mip-level will use non-mip-array spacing.
> 
> PRM Volume 2, Part 1, 7.5.3 Hierarchical Depth Buffer
>  "[DevSNB]: The hierarchical depth buffer does not support the LOD
>   field, it is assumed by hardware to be zero. A separate
>   hierarachical depth buffer is required for each LOD used, and the
>   corresponding buffer???s state delivered to hardware each time a new
>   depth buffer state with modified LOD is delivered."
> 
> We allocate storage for the other hiz mip-levels within a single
> texture, but each mip-level will use non-mip-array spacing.
> 
> Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 2a5afab..67cf515 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -331,8 +331,10 @@ intel_miptree_create_layout(struct brw_context *brw,
>        }
>     }
>  
> -   /* non_mip_arrays is only used for non-IMS MSAA surfaces.  TODO: can we
> -    * use it elsewhere?
> +   /* non_mip_arrays is only used for:
> +    * - non-IMS MSAA surfaces
> +    * - gen6 separate stencil
> +    * - gen6 hiz
>      */
>     switch (mt->msaa_layout) {
>     case INTEL_MSAA_LAYOUT_NONE:
> @@ -358,6 +360,7 @@ intel_miptree_create_layout(struct brw_context *brw,
>         _mesa_get_format_base_format(format) == GL_DEPTH_STENCIL &&
>         (brw->must_use_separate_stencil ||
>  	(brw->has_separate_stencil && brw_is_hiz_depth_format(brw, format)))) {
> +      bool force_non_mip_arrays = brw->gen == 6;

const

>        mt->stencil_mt = intel_miptree_create(brw,
>                                              mt->target,
>                                              MESA_FORMAT_S_UINT8,
> @@ -369,7 +372,7 @@ intel_miptree_create_layout(struct brw_context *brw,
>                                              true,
>                                              num_samples,
>                                              INTEL_MIPTREE_TILING_ANY,
> -                                            false);
> +                                            force_non_mip_arrays);
>        if (!mt->stencil_mt) {
>  	 intel_miptree_release(&mt);
>  	 return NULL;
> @@ -1386,6 +1389,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
>  			struct intel_mipmap_tree *mt)
>  {
>     assert(mt->hiz_mt == NULL);
> +   bool force_non_mip_arrays = brw->gen == 6;

const

>     mt->hiz_mt = intel_miptree_create(brw,
>                                       mt->target,
>                                       mt->format,
> @@ -1397,7 +1401,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
>                                       true,
>                                       mt->num_samples,
>                                       INTEL_MIPTREE_TILING_ANY,
> -                                     false);
> +                                     force_non_mip_arrays);
>  
>     if (!mt->hiz_mt)
>        return false;
> -- 
> 2.0.1
> 
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