[Mesa-dev] [PATCH] r600g: Implement GL_ARB_texture_query_lod

[Alex Deucher]

On Wed, Jul 23, 2014 at 4:48 AM, Glenn Kennard <glenn.kennard at gmail.com> wrote:
> Requires Evergreen or later

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
> Passes ARB_texture_query_lod piglits, no other regressions,
> tested on radeon 6670.
>
>  docs/GL3.txt                           |  2 +-
>  src/gallium/drivers/r600/r600_pipe.c   |  2 +-
>  src/gallium/drivers/r600/r600_shader.c | 13 ++++++++++++-
>  3 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/docs/GL3.txt b/docs/GL3.txt
> index 8128692..d481148 100644
> --- a/docs/GL3.txt
> +++ b/docs/GL3.txt
> @@ -119,7 +119,7 @@ GL 4.0:
>    GL_ARB_texture_buffer_object_rgb32                   DONE (i965, nvc0, r600, radeonsi, softpipe)
>    GL_ARB_texture_cube_map_array                        DONE (i965, nv50, nvc0, r600, radeonsi, softpipe)
>    GL_ARB_texture_gather                                DONE (i965, nv50, nvc0, radeonsi, r600)
> -  GL_ARB_texture_query_lod                             DONE (i965, nv50, nvc0, radeonsi)
> +  GL_ARB_texture_query_lod                             DONE (i965, nv50, nvc0, r600, radeonsi)
>    GL_ARB_transform_feedback2                           DONE (i965, nv50, nvc0, r600, radeonsi)
>    GL_ARB_transform_feedback3                           DONE (i965, nv50, nvc0, r600, radeonsi)
>
> diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
> index 5bf9c00..7c50169 100644
> --- a/src/gallium/drivers/r600/r600_pipe.c
> +++ b/src/gallium/drivers/r600/r600_pipe.c
> @@ -304,6 +304,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
>         case PIPE_CAP_CUBE_MAP_ARRAY:
>         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
>         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
> +       case PIPE_CAP_TEXTURE_QUERY_LOD:
>                 return family >= CHIP_CEDAR ? 1 : 0;
>
>         /* Unsupported features. */
> @@ -314,7 +315,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
>         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
>         case PIPE_CAP_USER_VERTEX_BUFFERS:
>         case PIPE_CAP_TEXTURE_GATHER_SM5:
> -       case PIPE_CAP_TEXTURE_QUERY_LOD:
>         case PIPE_CAP_SAMPLE_SHADING:
>         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
>         case PIPE_CAP_DRAW_INDIRECT:
> diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
> index db928f3..499e511 100644
> --- a/src/gallium/drivers/r600/r600_shader.c
> +++ b/src/gallium/drivers/r600/r600_shader.c
> @@ -5106,13 +5106,21 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
>                 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
>                 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
>                 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
> +               tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
> +       }
> +       else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
> +               tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
> +               tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
> +               tex.dst_sel_z = 7;
> +               tex.dst_sel_w = 7;
>         }
>         else {
>                 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
>                 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
>                 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
> +               tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
>         }
> -       tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
> +
>
>         if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
>                 tex.src_sel_x = 4;
> @@ -6669,6 +6677,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
>         {TGSI_OPCODE_IMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported},
>         {TGSI_OPCODE_UMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported},
>         {TGSI_OPCODE_TG4,   0, FETCH_OP_GATHER4, tgsi_unsupported},
> +       {TGSI_OPCODE_LODQ,      0, FETCH_OP_GET_LOD, tgsi_unsupported},
>         {TGSI_OPCODE_LAST,      0, ALU_OP0_NOP, tgsi_unsupported},
>  };
>
> @@ -6864,6 +6873,7 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
>         {TGSI_OPCODE_IMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported},
>         {TGSI_OPCODE_UMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported},
>         {TGSI_OPCODE_TG4,   0, FETCH_OP_GATHER4, tgsi_tex},
> +       {TGSI_OPCODE_LODQ,      0, FETCH_OP_GET_LOD, tgsi_tex},
>         {TGSI_OPCODE_LAST,      0, ALU_OP0_NOP, tgsi_unsupported},
>  };
>
> @@ -7060,5 +7070,6 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
>         {TGSI_OPCODE_IMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported},
>         {TGSI_OPCODE_UMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported},
>         {TGSI_OPCODE_TG4,   0, FETCH_OP_GATHER4, tgsi_tex},
> +       {TGSI_OPCODE_LODQ,      0, FETCH_OP_GET_LOD, tgsi_tex},
>         {TGSI_OPCODE_LAST,      0, ALU_OP0_NOP, tgsi_unsupported},
>  };
> --
> 1.8.3.2
>
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