[Mesa-dev] [PATCH 03/20] i965: Pass a cfg pointer to generate_{code, assembly}.
Matt Turner
mattst88 at gmail.com
Thu Jul 24 19:54:10 PDT 2014
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 4 +++-
src/mesa/drivers/dri/i965/brw_fs.cpp | 10 ++++++----
src/mesa/drivers/dri/i965/brw_fs.h | 12 ++++++------
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 22 +++++++++-------------
src/mesa/drivers/dri/i965/brw_vec4.cpp | 6 ++++--
src/mesa/drivers/dri/i965/brw_vec4.h | 8 ++++----
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 12 ++++--------
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 10 +++++-----
src/mesa/drivers/dri/i965/gen8_fs_generator.cpp | 22 +++++++++-------------
src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp | 12 ++++--------
src/mesa/drivers/dri/i965/intel_asm_annotation.c | 2 +-
src/mesa/drivers/dri/i965/intel_asm_annotation.h | 2 +-
12 files changed, 56 insertions(+), 66 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
index c1676a9..8fa2e0e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
@@ -24,6 +24,7 @@
#include "glsl/ralloc.h"
#include "brw_blorp_blit_eu.h"
#include "brw_blorp.h"
+#include "brw_cfg.h"
brw_blorp_eu_emitter::brw_blorp_eu_emitter(struct brw_context *brw,
bool debug_flag)
@@ -43,7 +44,8 @@ brw_blorp_eu_emitter::~brw_blorp_eu_emitter()
const unsigned *
brw_blorp_eu_emitter::get_program(unsigned *program_size)
{
- return generator.generate_assembly(NULL, &insts, program_size);
+ cfg_t cfg(&insts);
+ return generator.generate_assembly(NULL, &cfg, program_size);
}
/**
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 0d1185b..2fd700f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -3170,6 +3170,8 @@ fs_visitor::run()
*/
assert(sanity_param_count == fp->Base.Parameters->NumParameters);
+ calculate_cfg();
+
return !failed;
}
@@ -3213,7 +3215,7 @@ brw_wm_fs_emit(struct brw_context *brw,
return NULL;
}
- exec_list *simd16_instructions = NULL;
+ cfg_t *simd16_cfg = NULL;
fs_visitor v2(brw, mem_ctx, key, prog_data, prog, fp, 16);
if (brw->gen >= 5 && likely(!(INTEL_DEBUG & DEBUG_NO16))) {
if (!v.simd16_unsupported) {
@@ -3223,7 +3225,7 @@ brw_wm_fs_emit(struct brw_context *brw,
perf_debug("SIMD16 shader failed to compile, falling back to "
"SIMD8 at a 10-20%% performance cost: %s", v2.fail_msg);
} else {
- simd16_instructions = &v2.instructions;
+ simd16_cfg = v2.cfg;
}
} else {
perf_debug("SIMD16 shader unsupported, falling back to "
@@ -3234,12 +3236,12 @@ brw_wm_fs_emit(struct brw_context *brw,
const unsigned *assembly = NULL;
if (brw->gen >= 8) {
gen8_fs_generator g(brw, mem_ctx, key, prog_data, prog, fp, v.do_dual_src);
- assembly = g.generate_assembly(&v.instructions, simd16_instructions,
+ assembly = g.generate_assembly(v.cfg, simd16_cfg,
final_assembly_size);
} else {
fs_generator g(brw, mem_ctx, key, prog_data, prog, fp, v.do_dual_src,
v.runtime_check_aads_emit, INTEL_DEBUG & DEBUG_WM);
- assembly = g.generate_assembly(&v.instructions, simd16_instructions,
+ assembly = g.generate_assembly(v.cfg, simd16_cfg,
final_assembly_size);
}
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 9ba3f38..009a6d5 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -578,12 +578,12 @@ public:
bool debug_flag);
~fs_generator();
- const unsigned *generate_assembly(exec_list *simd8_instructions,
- exec_list *simd16_instructions,
+ const unsigned *generate_assembly(const cfg_t *simd8_cfg,
+ const cfg_t *simd16_cfg,
unsigned *assembly_size);
private:
- void generate_code(exec_list *instructions);
+ void generate_code(const cfg_t *cfg);
void fire_fb_write(fs_inst *inst,
GLuint base_reg,
struct brw_reg implied_header,
@@ -706,12 +706,12 @@ public:
bool dual_source_output);
~gen8_fs_generator();
- const unsigned *generate_assembly(exec_list *simd8_instructions,
- exec_list *simd16_instructions,
+ const unsigned *generate_assembly(const cfg_t *simd8_cfg,
+ const cfg_t *simd16_cfg,
unsigned *assembly_size);
private:
- void generate_code(exec_list *instructions);
+ void generate_code(const cfg_t *cfg);
void generate_fb_write(fs_inst *inst);
void generate_linterp(fs_inst *inst, struct brw_reg dst,
struct brw_reg *src);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 8e4a31d..a720670 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1325,18 +1325,14 @@ fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
}
void
-fs_generator::generate_code(exec_list *instructions)
+fs_generator::generate_code(const cfg_t *cfg)
{
int start_offset = p->next_insn_offset;
struct annotation_info annotation;
memset(&annotation, 0, sizeof(annotation));
- cfg_t *cfg = NULL;
- if (unlikely(debug_flag))
- cfg = new(mem_ctx) cfg_t(instructions);
-
- foreach_in_list(fs_inst, inst, instructions) {
+ foreach_block_and_inst (block, fs_inst, inst, cfg) {
struct brw_reg src[3], dst;
unsigned int last_insn_offset = p->next_insn_offset;
@@ -1831,18 +1827,18 @@ fs_generator::generate_code(exec_list *instructions)
}
const unsigned *
-fs_generator::generate_assembly(exec_list *simd8_instructions,
- exec_list *simd16_instructions,
+fs_generator::generate_assembly(const cfg_t *simd8_cfg,
+ const cfg_t *simd16_cfg,
unsigned *assembly_size)
{
- assert(simd8_instructions || simd16_instructions);
+ assert(simd8_cfg || simd16_cfg);
- if (simd8_instructions) {
+ if (simd8_cfg) {
dispatch_width = 8;
- generate_code(simd8_instructions);
+ generate_code(simd8_cfg);
}
- if (simd16_instructions) {
+ if (simd16_cfg) {
/* align to 64 byte boundary. */
while (p->next_insn_offset % 64) {
brw_NOP(p);
@@ -1854,7 +1850,7 @@ fs_generator::generate_assembly(exec_list *simd8_instructions,
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
dispatch_width = 16;
- generate_code(simd16_instructions);
+ generate_code(simd16_cfg);
}
return brw_get_program(p, assembly_size);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 73d114d..5f6526d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1742,6 +1742,8 @@ vec4_visitor::run()
*/
assert(sanity_param_count == prog->Parameters->NumParameters);
+ calculate_cfg();
+
return !failed;
}
@@ -1795,11 +1797,11 @@ brw_vs_emit(struct brw_context *brw,
if (brw->gen >= 8) {
gen8_vec4_generator g(brw, prog, &c->vp->program.Base, &prog_data->base,
mem_ctx, INTEL_DEBUG & DEBUG_VS);
- assembly = g.generate_assembly(&v.instructions, final_assembly_size);
+ assembly = g.generate_assembly(v.cfg, final_assembly_size);
} else {
vec4_generator g(brw, prog, &c->vp->program.Base, &prog_data->base,
mem_ctx, INTEL_DEBUG & DEBUG_VS);
- assembly = g.generate_assembly(&v.instructions, final_assembly_size);
+ assembly = g.generate_assembly(v.cfg, final_assembly_size);
}
if (unlikely(brw->perf_debug) && shader) {
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 3d0df77..7be27a0 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -624,10 +624,10 @@ public:
bool debug_flag);
~vec4_generator();
- const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
+ const unsigned *generate_assembly(const cfg_t *cfg, unsigned *asm_size);
private:
- void generate_code(exec_list *instructions);
+ void generate_code(const cfg_t *cfg);
void generate_vec4_instruction(vec4_instruction *inst,
struct brw_reg dst,
struct brw_reg *src);
@@ -718,10 +718,10 @@ public:
bool debug_flag);
~gen8_vec4_generator();
- const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
+ const unsigned *generate_assembly(const cfg_t *cfg, unsigned *asm_size);
private:
- void generate_code(exec_list *instructions);
+ void generate_code(const cfg_t *cfg);
void generate_vec4_instruction(vec4_instruction *inst,
struct brw_reg dst,
struct brw_reg *src);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 5266f81..79c2bf5 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -1221,16 +1221,12 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
}
void
-vec4_generator::generate_code(exec_list *instructions)
+vec4_generator::generate_code(const cfg_t *cfg)
{
struct annotation_info annotation;
memset(&annotation, 0, sizeof(annotation));
- cfg_t *cfg = NULL;
- if (unlikely(debug_flag))
- cfg = new(mem_ctx) cfg_t(instructions);
-
- foreach_in_list(vec4_instruction, inst, instructions) {
+ foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
struct brw_reg src[3], dst;
if (unlikely(debug_flag))
@@ -1290,11 +1286,11 @@ vec4_generator::generate_code(exec_list *instructions)
}
const unsigned *
-vec4_generator::generate_assembly(exec_list *instructions,
+vec4_generator::generate_assembly(const cfg_t *cfg,
unsigned *assembly_size)
{
brw_set_default_access_mode(p, BRW_ALIGN_16);
- generate_code(instructions);
+ generate_code(cfg);
return brw_get_program(p, assembly_size);
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index 75ea9a2..176de70 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -612,17 +612,17 @@ generate_assembly(struct brw_context *brw,
struct gl_program *prog,
struct brw_vec4_prog_data *prog_data,
void *mem_ctx,
- exec_list *instructions,
+ const cfg_t *cfg,
unsigned *final_assembly_size)
{
if (brw->gen >= 8) {
gen8_vec4_generator g(brw, shader_prog, prog, prog_data, mem_ctx,
INTEL_DEBUG & DEBUG_GS);
- return g.generate_assembly(instructions, final_assembly_size);
+ return g.generate_assembly(cfg, final_assembly_size);
} else {
vec4_generator g(brw, shader_prog, prog, prog_data, mem_ctx,
INTEL_DEBUG & DEBUG_GS);
- return g.generate_assembly(instructions, final_assembly_size);
+ return g.generate_assembly(cfg, final_assembly_size);
}
}
@@ -651,7 +651,7 @@ brw_gs_emit(struct brw_context *brw,
vec4_gs_visitor v(brw, c, prog, mem_ctx, true /* no_spills */);
if (v.run()) {
return generate_assembly(brw, prog, &c->gp->program.Base,
- &c->prog_data.base, mem_ctx, &v.instructions,
+ &c->prog_data.base, mem_ctx, v.cfg,
final_assembly_size);
}
}
@@ -676,7 +676,7 @@ brw_gs_emit(struct brw_context *brw,
}
return generate_assembly(brw, prog, &c->gp->program.Base, &c->prog_data.base,
- mem_ctx, &v.instructions, final_assembly_size);
+ mem_ctx, v.cfg, final_assembly_size);
}
diff --git a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
index 4f0cf70..e33f412 100644
--- a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
@@ -875,18 +875,14 @@ gen8_fs_generator::generate_untyped_surface_read(fs_inst *ir,
}
void
-gen8_fs_generator::generate_code(exec_list *instructions)
+gen8_fs_generator::generate_code(const cfg_t *cfg)
{
int start_offset = next_inst_offset;
struct annotation_info annotation;
memset(&annotation, 0, sizeof(annotation));
- cfg_t *cfg = NULL;
- if (unlikely(INTEL_DEBUG & DEBUG_WM))
- cfg = new(mem_ctx) cfg_t(instructions);
-
- foreach_in_list(fs_inst, ir, instructions) {
+ foreach_block_and_inst (block, fs_inst, ir, cfg) {
struct brw_reg src[3], dst;
if (unlikely(INTEL_DEBUG & DEBUG_WM))
@@ -1265,18 +1261,18 @@ gen8_fs_generator::generate_code(exec_list *instructions)
}
const unsigned *
-gen8_fs_generator::generate_assembly(exec_list *simd8_instructions,
- exec_list *simd16_instructions,
+gen8_fs_generator::generate_assembly(const cfg_t *simd8_cfg,
+ const cfg_t *simd16_cfg,
unsigned *assembly_size)
{
- assert(simd8_instructions || simd16_instructions);
+ assert(simd8_cfg || simd16_cfg);
- if (simd8_instructions) {
+ if (simd8_cfg) {
dispatch_width = 8;
- generate_code(simd8_instructions);
+ generate_code(simd8_cfg);
}
- if (simd16_instructions) {
+ if (simd16_cfg) {
/* Align to a 64-byte boundary. */
while (next_inst_offset % 64)
NOP();
@@ -1285,7 +1281,7 @@ gen8_fs_generator::generate_assembly(exec_list *simd8_instructions,
prog_data->prog_offset_16 = next_inst_offset;
dispatch_width = 16;
- generate_code(simd16_instructions);
+ generate_code(simd16_cfg);
}
*assembly_size = next_inst_offset;
diff --git a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
index 4f9b2a3..4b249df 100644
--- a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
@@ -839,16 +839,12 @@ gen8_vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
}
void
-gen8_vec4_generator::generate_code(exec_list *instructions)
+gen8_vec4_generator::generate_code(const cfg_t *cfg)
{
struct annotation_info annotation;
memset(&annotation, 0, sizeof(annotation));
- cfg_t *cfg = NULL;
- if (unlikely(debug_flag))
- cfg = new(mem_ctx) cfg_t(instructions);
-
- foreach_in_list(vec4_instruction, ir, instructions) {
+ foreach_block_and_inst (block, vec4_instruction, ir, cfg) {
struct brw_reg src[3], dst;
if (unlikely(debug_flag))
@@ -900,12 +896,12 @@ gen8_vec4_generator::generate_code(exec_list *instructions)
}
const unsigned *
-gen8_vec4_generator::generate_assembly(exec_list *instructions,
+gen8_vec4_generator::generate_assembly(const cfg_t *cfg,
unsigned *assembly_size)
{
default_state.access_mode = BRW_ALIGN_16;
default_state.exec_size = BRW_EXECUTE_8;
- generate_code(instructions);
+ generate_code(cfg);
*assembly_size = next_inst_offset;
return (const unsigned *) store;
diff --git a/src/mesa/drivers/dri/i965/intel_asm_annotation.c b/src/mesa/drivers/dri/i965/intel_asm_annotation.c
index 5aee458..953a60a 100644
--- a/src/mesa/drivers/dri/i965/intel_asm_annotation.c
+++ b/src/mesa/drivers/dri/i965/intel_asm_annotation.c
@@ -92,7 +92,7 @@ dump_assembly(void *assembly, int num_annotations, struct annotation *annotation
}
void annotate(struct brw_context *brw,
- struct annotation_info *annotation, struct cfg_t *cfg,
+ struct annotation_info *annotation, const struct cfg_t *cfg,
struct backend_instruction *inst, unsigned offset)
{
if (annotation->ann_size <= annotation->ann_count) {
diff --git a/src/mesa/drivers/dri/i965/intel_asm_annotation.h b/src/mesa/drivers/dri/i965/intel_asm_annotation.h
index 79f3372..d80f320 100644
--- a/src/mesa/drivers/dri/i965/intel_asm_annotation.h
+++ b/src/mesa/drivers/dri/i965/intel_asm_annotation.h
@@ -64,7 +64,7 @@ dump_assembly(void *assembly, int num_annotations, struct annotation *annotation
void
annotate(struct brw_context *brw,
- struct annotation_info *annotation, struct cfg_t *cfg,
+ struct annotation_info *annotation, const struct cfg_t *cfg,
struct backend_instruction *inst, unsigned offset);
void
annotation_finalize(struct annotation_info *annotation, unsigned offset);
--
1.8.5.5
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