[Mesa-dev] [RFC 1/7] i965: Refactor render target type resolving
Topi Pohjolainen
topi.pohjolainen at intel.com
Wed Jul 30 10:03:57 PDT 2014
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_state.h | 8 ++++++++
src/mesa/drivers/dri/i965/gen6_depth_state.c | 8 +++-----
src/mesa/drivers/dri/i965/gen6_surface_state.c | 3 +--
src/mesa/drivers/dri/i965/gen7_misc_state.c | 8 +++-----
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 4 +---
src/mesa/drivers/dri/i965/gen8_depth_state.c | 8 +++-----
src/mesa/drivers/dri/i965/gen8_surface_state.c | 3 +--
7 files changed, 20 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 8e176f3..a17157a 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -151,6 +151,14 @@ extern const struct brw_tracked_state gen8_vertices;
extern const struct brw_tracked_state gen8_vf_topology;
extern const struct brw_tracked_state gen8_vs_state;
+inline static GLenum
+brw_get_target(const struct gl_renderbuffer *rb)
+{
+ if (!rb || !rb->TexImage)
+ return GL_TEXTURE_2D;
+ return rb->TexImage->TexObject->Target;
+}
+
/* brw_misc_state.c */
void brw_upload_invariant_state(struct brw_context *brw);
uint32_t
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index fd37594..1a8df99 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -49,7 +49,6 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
uint32_t surftype;
unsigned int depth = 1;
unsigned int min_array_element;
- GLenum gl_target = GL_TEXTURE_2D;
unsigned int lod;
const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
const struct intel_renderbuffer *irb = NULL;
@@ -80,11 +79,10 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
rb = (struct gl_renderbuffer*) irb;
- if (rb) {
+ const GLenum gl_target = brw_get_target(rb);
+
+ if (rb)
depth = MAX2(rb->Depth, 1);
- if (rb->TexImage)
- gl_target = rb->TexImage->TexObject->Target;
- }
switch (gl_target) {
case GL_TEXTURE_CUBE_MAP_ARRAY:
diff --git a/src/mesa/drivers/dri/i965/gen6_surface_state.c b/src/mesa/drivers/dri/i965/gen6_surface_state.c
index 29a4800..ef13d3d 100644
--- a/src/mesa/drivers/dri/i965/gen6_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_surface_state.c
@@ -58,10 +58,9 @@ gen6_update_renderbuffer_surface(struct brw_context *brw,
uint32_t format = 0;
/* _NEW_BUFFERS */
mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
+ const GLenum gl_target = brw_get_target(rb);
uint32_t surftype;
int depth = MAX2(rb->Depth, 1);
- GLenum gl_target = rb->TexImage ?
- rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
uint32_t surf_index =
brw->wm.prog_data->binding_table.render_target_start + unit;
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 22911bf..1419364 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -45,7 +45,6 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
uint32_t surftype;
unsigned int depth = 1;
unsigned int min_array_element;
- GLenum gl_target = GL_TEXTURE_2D;
unsigned int lod;
const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
const struct intel_renderbuffer *irb = NULL;
@@ -64,11 +63,10 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
rb = (struct gl_renderbuffer*) irb;
- if (rb) {
+ const GLenum gl_target = brw_get_target(rb);
+
+ if (rb)
depth = MAX2(irb->layer_count, 1);
- if (rb->TexImage)
- gl_target = rb->TexImage->TexObject->Target;
- }
switch (gl_target) {
case GL_TEXTURE_CUBE_MAP_ARRAY:
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 5d068d4..89d92ab 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -461,6 +461,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
uint32_t format;
/* _NEW_BUFFERS */
mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
+ const GLenum gl_target = brw_get_target(rb);
uint32_t surftype;
bool is_array = false;
int depth = MAX2(irb->layer_count, 1);
@@ -468,9 +469,6 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
int min_array_element = irb->mt_layer / MAX2(mt->num_samples, 1);
- GLenum gl_target = rb->TexImage ?
- rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
-
uint32_t surf_index =
brw->wm.prog_data->binding_table.render_target_start + unit;
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 7c3bfe0..96e722b 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -156,7 +156,6 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
uint32_t surftype;
unsigned int depth = 1;
unsigned int min_array_element;
- GLenum gl_target = GL_TEXTURE_2D;
unsigned int lod;
const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
const struct intel_renderbuffer *irb = NULL;
@@ -167,11 +166,10 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
rb = (struct gl_renderbuffer *) irb;
- if (rb) {
+ const GLenum gl_target = brw_get_target(rb);
+
+ if (rb)
depth = MAX2(irb->layer_count, 1);
- if (rb->TexImage)
- gl_target = rb->TexImage->TexObject->Target;
- }
switch (gl_target) {
case GL_TEXTURE_CUBE_MAP_ARRAY:
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 40eb2ea..5575aa4 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -309,6 +309,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_mipmap_tree *mt = irb->mt;
struct intel_mipmap_tree *aux_mt = NULL;
+ const GLenum gl_target = brw_get_target(rb);
uint32_t aux_mode = 0;
unsigned width = mt->logical_width0;
unsigned height = mt->logical_height0;
@@ -320,8 +321,6 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
int depth = MAX2(irb->layer_count, 1);
const int min_array_element = (mt->format == MESA_FORMAT_S_UINT8) ?
irb->mt_layer : (irb->mt_layer / MAX2(mt->num_samples, 1));
- GLenum gl_target =
- rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
uint32_t surf_index =
brw->wm.prog_data->binding_table.render_target_start + unit;
--
1.8.3.1
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