[Mesa-dev] [RFC 7/7] i965: Merge common bits of gen7/8 renderbuffer surface setup
Topi Pohjolainen
topi.pohjolainen at intel.com
Wed Jul 30 10:04:03 PDT 2014
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_state.h | 3 +
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 119 ++++++++++++----------
src/mesa/drivers/dri/i965/gen8_surface_state.c | 59 +----------
3 files changed, 73 insertions(+), 108 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 58ce614..6265b73 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -252,6 +252,9 @@ void gen7_set_surface_mcs_info(struct brw_context *brw,
bool is_render_target);
void gen7_check_surface_setup(uint32_t *surf, bool is_render_target);
void gen7_init_vtable_surface_functions(struct brw_context *brw);
+void gen7_set_render_surface_common(struct brw_context *brw,
+ struct gl_renderbuffer *rb,
+ uint32_t *surf);
/* gen7_sol_state.c */
void gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index be10d5d..3ff6274 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -264,6 +264,72 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
gen7_check_surface_setup(surf, false /* is_render_target */);
}
+void
+gen7_set_render_surface_common(struct brw_context *brw,
+ struct gl_renderbuffer *rb,
+ uint32_t *surf)
+{
+ struct gl_context *ctx = &brw->ctx;
+ const struct intel_renderbuffer *irb = intel_renderbuffer(rb);
+ struct intel_mipmap_tree *mt = irb->mt;
+ const GLenum gl_target = brw_get_target(rb);
+ const int depth = intel_rb_adjust_depth(brw, irb, mt, gl_target);
+ const uint32_t surf_type = brw_get_surface_type(gl_target);
+ unsigned width = mt->logical_width0;
+ unsigned height = mt->logical_height0;
+ unsigned pitch = mt->pitch;
+ uint32_t tiling = mt->tiling;
+ uint32_t format = 0;
+ const int min_array_element = (mt->format == MESA_FORMAT_S_UINT8) ?
+ irb->mt_layer : (irb->mt_layer / MAX2(mt->num_samples, 1));
+
+ intel_miptree_used_for_rendering(mt);
+
+ /* _NEW_BUFFERS */
+ /* Render targets can't use IMS layout. Stencil in turn gets configured as
+ * single sampled and indexed manually by the program.
+ */
+ if (mt->format == MESA_FORMAT_S_UINT8) {
+ assert(brw->gen >= 8);
+ brw_configure_w_tiled(mt, true, &width, &height, &pitch,
+ &tiling, &format);
+ } else {
+ assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
+ assert(brw_render_target_supported(brw, rb));
+ mesa_format rb_format = _mesa_get_render_format(ctx,
+ intel_rb_format(irb));
+ format = brw->render_target_format[rb_format];
+ if (unlikely(!brw->format_supported_as_render_target[rb_format]))
+ _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
+ __FUNCTION__, _mesa_get_format_name(rb_format));
+ }
+
+ surf[0] = SET_FIELD(surf_type, BRW_SURFACE_TYPE) |
+ (brw_is_array(gl_target) ? GEN7_SURFACE_IS_ARRAY : 0) |
+ SET_FIELD(format, BRW_SURFACE_FORMAT) |
+ gen7_surface_tiling_mode(brw->gen, tiling);
+
+ surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
+ SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
+ surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) | (pitch - 1);
+ surf[4] = SET_FIELD(min_array_element, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
+ SET_FIELD(depth - 1, GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
+
+ if (mt->format != MESA_FORMAT_S_UINT8)
+ surf[4] |= gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
+
+ surf[5] = irb->mt_level - irb->mt->first_level;
+
+ surf[7] = irb->mt->fast_clear_color_value;
+
+ if (brw->gen >= 8 || brw->is_haswell) {
+ surf[7] |= (SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
+ SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
+ SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
+ SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
+ }
+}
+
static void
gen7_update_texture_surface(struct gl_context *ctx,
unsigned unit,
@@ -455,19 +521,9 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
bool layered,
unsigned int unit)
{
- struct gl_context *ctx = &brw->ctx;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_mipmap_tree *mt = irb->mt;
- uint32_t format;
- /* _NEW_BUFFERS */
- mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
- const GLenum gl_target = brw_get_target(rb);
- const int depth = intel_rb_adjust_depth(brw, irb, mt, gl_target);
- const uint32_t surftype = brw_get_surface_type(gl_target);
const uint8_t mocs = GEN7_MOCS_L3;
-
- int min_array_element = irb->mt_layer / MAX2(mt->num_samples, 1);
-
uint32_t surf_index =
brw->wm.prog_data->binding_table.render_target_start + unit;
@@ -475,63 +531,24 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
&brw->wm.base.surf_offset[surf_index]);
memset(surf, 0, 8 * 4);
- intel_miptree_used_for_rendering(irb->mt);
-
- /* Render targets can't use IMS layout */
- assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
-
- assert(brw_render_target_supported(brw, rb));
- format = brw->render_target_format[rb_format];
- if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
- _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
- __FUNCTION__, _mesa_get_format_name(rb_format));
- }
-
- surf[0] = surftype << BRW_SURFACE_TYPE_SHIFT |
- format << BRW_SURFACE_FORMAT_SHIFT |
- (irb->mt->non_mip_arrays ? GEN7_SURFACE_ARYSPC_LOD0
- : GEN7_SURFACE_ARYSPC_FULL) |
- gen7_surface_tiling_mode(brw->gen, mt->tiling);
+ gen7_set_render_surface_common(brw, rb, surf);
if (irb->mt->align_h == 4)
surf[0] |= GEN7_SURFACE_VALIGN_4;
if (irb->mt->align_w == 8)
surf[0] |= GEN7_SURFACE_HALIGN_8;
- if (brw_is_array(gl_target))
- surf[0] |= GEN7_SURFACE_IS_ARRAY;
-
surf[1] = mt->bo->offset64;
assert(brw->has_surface_tile_offset);
- surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS) |
- (irb->mt_level - irb->mt->first_level);
-
- surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
- SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
-
- surf[3] = ((depth - 1) << BRW_SURFACE_DEPTH_SHIFT) |
- (mt->pitch - 1);
-
- surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples, irb->mt->msaa_layout) |
- min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
- (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
+ surf[5] |= SET_FIELD(mocs, GEN7_SURFACE_MOCS);
if (irb->mt->mcs_mt) {
gen7_set_surface_mcs_info(brw, surf, brw->wm.base.surf_offset[surf_index],
irb->mt->mcs_mt, true /* is RT */);
}
- surf[7] = irb->mt->fast_clear_color_value;
-
- if (brw->is_haswell) {
- surf[7] |= (SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
- SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
- SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
- SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
- }
-
drm_intel_bo_emit_reloc(brw->batch.bo,
brw->wm.base.surf_offset[surf_index] + 4,
mt->bo,
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 107be01..8d87b79 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -305,45 +305,14 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
bool layered,
unsigned unit)
{
- struct gl_context *ctx = &brw->ctx;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_mipmap_tree *mt = irb->mt;
struct intel_mipmap_tree *aux_mt = NULL;
- const GLenum gl_target = brw_get_target(rb);
- const int depth = intel_rb_adjust_depth(brw, irb, mt, gl_target);
- const uint32_t surf_type = brw_get_surface_type(gl_target);
uint32_t aux_mode = 0;
- unsigned width = mt->logical_width0;
- unsigned height = mt->logical_height0;
- unsigned pitch = mt->pitch;
- uint32_t tiling = mt->tiling;
- uint32_t format = 0;
- const int min_array_element = (mt->format == MESA_FORMAT_S_UINT8) ?
- irb->mt_layer : (irb->mt_layer / MAX2(mt->num_samples, 1));
uint32_t surf_index =
brw->wm.prog_data->binding_table.render_target_start + unit;
- intel_miptree_used_for_rendering(mt);
-
- /* _NEW_BUFFERS */
- /* Render targets can't use IMS layout. Stencil in turn gets configured as
- * single sampled and indexed manually by the program.
- */
- if (mt->format == MESA_FORMAT_S_UINT8) {
- brw_configure_w_tiled(mt, true, &width, &height, &pitch,
- &tiling, &format);
- } else {
- assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
- assert(brw_render_target_supported(brw, rb));
- mesa_format rb_format = _mesa_get_render_format(ctx,
- intel_rb_format(irb));
- format = brw->render_target_format[rb_format];
- if (unlikely(!brw->format_supported_as_render_target[rb_format]))
- _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
- __FUNCTION__, _mesa_get_format_name(rb_format));
- }
-
if (mt->mcs_mt) {
aux_mt = mt->mcs_mt;
aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
@@ -352,29 +321,11 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 13 * 4, 64,
&brw->wm.base.surf_offset[surf_index]);
- surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) |
- (brw_is_array(gl_target) ? GEN7_SURFACE_IS_ARRAY : 0) |
- (format << BRW_SURFACE_FORMAT_SHIFT) |
- vertical_alignment(mt) |
- horizontal_alignment(mt) |
- surface_tiling_mode(tiling);
+ gen7_set_render_surface_common(brw, rb, surf);
+ surf[0] |= vertical_alignment(mt) | horizontal_alignment(mt);
surf[1] = SET_FIELD(BDW_MOCS_WT, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
- surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
- SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
-
- surf[3] = (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
- (pitch - 1); /* Surface Pitch */
-
- surf[4] = min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
- (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
-
- if (mt->format != MESA_FORMAT_S_UINT8)
- surf[4] |= gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
-
- surf[5] = irb->mt_level - irb->mt->first_level;
-
if (aux_mt) {
surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |
@@ -383,12 +334,6 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
surf[6] = 0;
}
- surf[7] = mt->fast_clear_color_value |
- SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
- SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
- SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
- SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
-
*((uint64_t *) &surf[8]) = mt->bo->offset64; /* reloc */
if (aux_mt) {
--
1.8.3.1
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