[Mesa-dev] [PATCH v3 0/4] Some register allocator cleanups and optimizations

[Connor Abbott]

This patch series contains some improvements to the register allocator
used by the i965 fs and vec4 backends and r300g. The most important
patch is the last one, which causes many fragment shaders to gain SIMD16
as we make smarter decisions in the allocator. Full shader-db results
are reproduced in the last commit message, but here's the summary for
the whole series:

total instructions in shared programs: 4545447 -> 4545401 (-0.00%)
instructions in affected programs:     1353 -> 1307 (-3.40%)
GAINED:                                124
LOST:                                  6

v2: fix trailing whitespace, split the last patch in two
v3: rewrite patch 3, removing regressions in number of instructions

Connor Abbott (4):
  ra: cleanup the public API
  ra: make the p, q test more efficient
  ra: don't consider nodes for spilling we don't need to
  ra: optimistically color only one node at a time

 .../drivers/r300/compiler/radeon_pair_regalloc.c   |   2 +-
 src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp  |   2 +-
 .../drivers/dri/i965/brw_vec4_reg_allocate.cpp     |   2 +-
 src/mesa/program/register_allocate.c               | 145 +++++++++------------
 src/mesa/program/register_allocate.h               |   5 +-
 5 files changed, 65 insertions(+), 91 deletions(-)

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1.9.3