[Mesa-dev] [PATCH 15/22] i965/gen6: Add tile offset support for texture surfaces

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 30db9f9..0f596e4 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -331,6 +331,7 @@ brw_update_texture_surface(struct gl_context *ctx,
    uint32_t tiling = mt->tiling;
    unsigned min_lod = tObj->BaseLevel - mt->first_level;
    unsigned mip_count = intelObj->_MaxLevel - tObj->BaseLevel;
+   uint32_t tile_x = 0, tile_y = 0, page_offset = 0;
 
    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 			  6 * 4, 32, surf_offset);
@@ -381,7 +382,7 @@ brw_update_texture_surface(struct gl_context *ctx,
 	      BRW_SURFACE_CUBEFACE_ENABLES |
 	      tex_format << BRW_SURFACE_FORMAT_SHIFT);
 
-   surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
+   surf[1] = mt->bo->offset64 + mt->offset + page_offset; /* reloc */
 
    surf[2] = SET_FIELD(mip_count, BRW_SURFACE_LOD) |
              SET_FIELD(width - 1, BRW_SURFACE_WIDTH) |
@@ -400,7 +401,9 @@ brw_update_texture_surface(struct gl_context *ctx,
    if (!is_stencil(mt))
       surf[4] |= brw_get_surface_num_multisamples(mt->num_samples);
 
-   surf[5] = mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
+   surf[5] = (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0) |
+             SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
+             SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET);
 
    /* Emit relocation to surface contents */
    drm_intel_bo_emit_reloc(brw->batch.bo,
-- 
1.8.3.1