[Mesa-dev] [PATCH 16/22] i965/gen6: Offset stencil texture surfaces directly to level/layer

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 27 +++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 0f596e4..eba209a 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -305,6 +305,30 @@ brw_update_buffer_texture_surface(struct gl_context *ctx,
                                        false /* rw */);
 }
 
+static uint32_t
+compute_stencil_offsets(const struct brw_context *brw,
+                        const struct intel_mipmap_tree *mt,
+                        uint32_t *tile_x, uint32_t *tile_y)
+{
+   const unsigned layer = brw->meta_blit.is_active ?
+                             brw->meta_blit.src_layer : 0;
+   unsigned x_off, y_off;
+   uint32_t mask_x, mask_y;
+
+   intel_miptree_get_image_offset(mt, mt->first_level, layer, &x_off, &y_off);
+   intel_miptree_get_tile_masks(mt, &mask_x, &mask_y, true);
+
+   *tile_x = x_off & mask_x;
+   *tile_y = y_off & mask_y;
+
+   assert(*tile_x % 4 == 0);
+   assert(*tile_y % 2 == 0);
+
+   return intel_miptree_get_aligned_offset(mt,
+                                           x_off & ~mask_x, y_off & ~mask_y,
+                                           true);
+}
+
 static void
 brw_update_texture_surface(struct gl_context *ctx,
                            unsigned unit,
@@ -344,8 +368,9 @@ brw_update_texture_surface(struct gl_context *ctx,
          mt = mt->stencil_mt;
       brw_configure_w_tiled(mt, false, &width, &height, &pitch,
                             &tiling, &tex_format);
-      min_lod = mt->first_level;
+      min_lod = 0;
       mip_count = 0;
+      page_offset = compute_stencil_offsets(brw, mt, &tile_x, &tile_y);
    }
 
    if (for_gather) {
-- 
1.8.3.1