[Mesa-dev] [PATCH 1/3] i965: Disassemble 3-src operands widths' correctly.
Matt Turner
mattst88 at gmail.com
Sat Mar 8 12:45:59 PST 2014
<4,1,1> isn't a real thing. We meant <4,4,1>, i.e., each component of
the whole register.
---
src/mesa/drivers/dri/i965/brw_disasm.c | 6 +--
.../drivers/dri/i965/brw_schedule_instructions.cpp | 16 ++++----
src/mesa/drivers/dri/i965/gen8_disasm.c | 6 +--
.../drivers/dri/i965/test_blorp_blit_eu_gen.cpp | 48 +++++++++++-----------
4 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index 08263d5..913e04d 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -740,7 +740,7 @@ static int src0_3src (FILE *file, struct brw_instruction *inst)
return 0;
if (inst->bits2.da3src.src0_subreg_nr)
format (file, ".%d", inst->bits2.da3src.src0_subreg_nr);
- string (file, "<4,1,1>");
+ string (file, "<4,4,1>");
err |= control (file, "src da16 reg type", three_source_reg_encoding,
inst->bits1.da3src.src_type, NULL);
/*
@@ -792,7 +792,7 @@ static int src1_3src (FILE *file, struct brw_instruction *inst)
return 0;
if (src1_subreg_nr)
format (file, ".%d", src1_subreg_nr);
- string (file, "<4,1,1>");
+ string (file, "<4,4,1>");
err |= control (file, "src da16 reg type", three_source_reg_encoding,
inst->bits1.da3src.src_type, NULL);
/*
@@ -843,7 +843,7 @@ static int src2_3src (FILE *file, struct brw_instruction *inst)
return 0;
if (inst->bits3.da3src.src2_subreg_nr)
format (file, ".%d", inst->bits3.da3src.src2_subreg_nr);
- string (file, "<4,1,1>");
+ string (file, "<4,4,1>");
err |= control (file, "src da16 reg type", three_source_reg_encoding,
inst->bits1.da3src.src_type, NULL);
/*
diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 32f30ba..5449c1b 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -132,20 +132,20 @@ schedule_node::set_latency_gen7(bool is_haswell)
case BRW_OPCODE_MAD:
/* 2 cycles
* (since the last two src operands are in different register banks):
- * mad(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g3.1<4,1,1>F.x { align16 WE_normal 1Q };
+ * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
*
* 3 cycles on IVB, 4 on HSW
* (since the last two src operands are in the same register bank):
- * mad(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g2.1<4,1,1>F.x { align16 WE_normal 1Q };
+ * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
*
* 18 cycles on IVB, 16 on HSW
* (since the last two src operands are in different register banks):
- * mad(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g3.1<4,1,1>F.x { align16 WE_normal 1Q };
+ * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
* mov(8) null g4<4,5,1>F { align16 WE_normal 1Q };
*
* 20 cycles on IVB, 18 on HSW
* (since the last two src operands are in the same register bank):
- * mad(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g2.1<4,1,1>F.x { align16 WE_normal 1Q };
+ * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
* mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
*/
@@ -158,20 +158,20 @@ schedule_node::set_latency_gen7(bool is_haswell)
case BRW_OPCODE_LRP:
/* 2 cycles
* (since the last two src operands are in different register banks):
- * lrp(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g3.1<4,1,1>F.x { align16 WE_normal 1Q };
+ * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
*
* 3 cycles on IVB, 4 on HSW
* (since the last two src operands are in the same register bank):
- * lrp(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g2.1<4,1,1>F.x { align16 WE_normal 1Q };
+ * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
*
* 16 cycles on IVB, 14 on HSW
* (since the last two src operands are in different register banks):
- * lrp(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g3.1<4,1,1>F.x { align16 WE_normal 1Q };
+ * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
* mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
*
* 16 cycles
* (since the last two src operands are in the same register bank):
- * lrp(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g2.1<4,1,1>F.x { align16 WE_normal 1Q };
+ * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
* mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
*/
diff --git a/src/mesa/drivers/dri/i965/gen8_disasm.c b/src/mesa/drivers/dri/i965/gen8_disasm.c
index e63babd..8a5d1e0 100644
--- a/src/mesa/drivers/dri/i965/gen8_disasm.c
+++ b/src/mesa/drivers/dri/i965/gen8_disasm.c
@@ -569,7 +569,7 @@ src0_3src(FILE *file, struct gen8_instruction *inst)
return 0;
if (gen8_src0_3src_subreg_nr(inst))
format(file, ".%d", gen8_src0_3src_subreg_nr(inst));
- string(file, "<4,1,1>");
+ string(file, "<4,4,1>");
err |= control(file, "src da16 reg type", m_three_source_reg_encoding,
gen8_src_3src_type(inst), NULL);
err |= src_swizzle(file, swz_x, swz_y, swz_z, swz_w);
@@ -595,7 +595,7 @@ src1_3src(FILE *file, struct gen8_instruction *inst)
return 0;
if (src1_subreg_nr)
format(file, ".%d", src1_subreg_nr);
- string(file, "<4,1,1>");
+ string(file, "<4,4,1>");
err |= control(file, "src da16 reg type", m_three_source_reg_encoding,
gen8_src_3src_type(inst), NULL);
err |= src_swizzle(file, swz_x, swz_y, swz_z, swz_w);
@@ -620,7 +620,7 @@ src2_3src(FILE *file, struct gen8_instruction *inst)
return 0;
if (gen8_src2_3src_subreg_nr(inst))
format(file, ".%d", gen8_src2_3src_subreg_nr(inst));
- string(file, "<4,1,1>");
+ string(file, "<4,4,1>");
err |= control(file, "src da16 reg type", m_three_source_reg_encoding,
gen8_src_3src_type(inst), NULL);
err |= src_swizzle(file, swz_x, swz_y, swz_z, swz_w);
diff --git a/src/mesa/drivers/dri/i965/test_blorp_blit_eu_gen.cpp b/src/mesa/drivers/dri/i965/test_blorp_blit_eu_gen.cpp
index 9f9e0c2..aff477b 100644
--- a/src/mesa/drivers/dri/i965/test_blorp_blit_eu_gen.cpp
+++ b/src/mesa/drivers/dri/i965/test_blorp_blit_eu_gen.cpp
@@ -263,30 +263,30 @@ test_gen7_blend_scaled_msaa_8(struct brw_context *brw)
"0x000009e0: mov(16) g118<1>UD g46<8,8,1>UD { align1 WE_normal 1H };\n"
"0x000009f0: send(16) g28<1>UW g114<8,8,1>F\n"
" sampler (0, 0, 31, 2) mlen 6 rlen 8 { align1 WE_normal 1H };\n"
- "0x00000a00: lrp(8) g20<1>F g56<4,1,1>F g28<4,1,1>F g20<4,1,1>F { align16 WE_normal 1Q };\n"
- "0x00000a10: lrp(8) g21<1>F g57<4,1,1>F g29<4,1,1>F g21<4,1,1>F { align16 WE_normal 2Q };\n"
- "0x00000a20: lrp(8) g22<1>F g56<4,1,1>F g30<4,1,1>F g22<4,1,1>F { align16 WE_normal 1Q };\n"
- "0x00000a30: lrp(8) g23<1>F g57<4,1,1>F g31<4,1,1>F g23<4,1,1>F { align16 WE_normal 2Q };\n"
- "0x00000a40: lrp(8) g24<1>F g56<4,1,1>F g32<4,1,1>F g24<4,1,1>F { align16 WE_normal 1Q };\n"
- "0x00000a50: lrp(8) g25<1>F g57<4,1,1>F g33<4,1,1>F g25<4,1,1>F { align16 WE_normal 2Q };\n"
- "0x00000a60: lrp(8) g26<1>F g56<4,1,1>F g34<4,1,1>F g26<4,1,1>F { align16 WE_normal 1Q };\n"
- "0x00000a70: lrp(8) g27<1>F g57<4,1,1>F g35<4,1,1>F g27<4,1,1>F { align16 WE_normal 2Q };\n"
- "0x00000a80: lrp(8) g4<1>F g56<4,1,1>F g12<4,1,1>F g4<4,1,1>F { align16 WE_normal 1Q };\n"
- "0x00000a90: lrp(8) g5<1>F g57<4,1,1>F g13<4,1,1>F g5<4,1,1>F { align16 WE_normal 2Q };\n"
- "0x00000aa0: lrp(8) g6<1>F g56<4,1,1>F g14<4,1,1>F g6<4,1,1>F { align16 WE_normal 1Q };\n"
- "0x00000ab0: lrp(8) g7<1>F g57<4,1,1>F g15<4,1,1>F g7<4,1,1>F { align16 WE_normal 2Q };\n"
- "0x00000ac0: lrp(8) g8<1>F g56<4,1,1>F g16<4,1,1>F g8<4,1,1>F { align16 WE_normal 1Q };\n"
- "0x00000ad0: lrp(8) g9<1>F g57<4,1,1>F g17<4,1,1>F g9<4,1,1>F { align16 WE_normal 2Q };\n"
- "0x00000ae0: lrp(8) g10<1>F g56<4,1,1>F g18<4,1,1>F g10<4,1,1>F { align16 WE_normal 1Q };\n"
- "0x00000af0: lrp(8) g11<1>F g57<4,1,1>F g19<4,1,1>F g11<4,1,1>F { align16 WE_normal 2Q };\n"
- "0x00000b00: lrp(8) g4<1>F g58<4,1,1>F g20<4,1,1>F g4<4,1,1>F { align16 WE_normal 1Q };\n"
- "0x00000b10: lrp(8) g5<1>F g59<4,1,1>F g21<4,1,1>F g5<4,1,1>F { align16 WE_normal 2Q };\n"
- "0x00000b20: lrp(8) g6<1>F g58<4,1,1>F g22<4,1,1>F g6<4,1,1>F { align16 WE_normal 1Q };\n"
- "0x00000b30: lrp(8) g7<1>F g59<4,1,1>F g23<4,1,1>F g7<4,1,1>F { align16 WE_normal 2Q };\n"
- "0x00000b40: lrp(8) g8<1>F g58<4,1,1>F g24<4,1,1>F g8<4,1,1>F { align16 WE_normal 1Q };\n"
- "0x00000b50: lrp(8) g9<1>F g59<4,1,1>F g25<4,1,1>F g9<4,1,1>F { align16 WE_normal 2Q };\n"
- "0x00000b60: lrp(8) g10<1>F g58<4,1,1>F g26<4,1,1>F g10<4,1,1>F { align16 WE_normal 1Q };\n"
- "0x00000b70: lrp(8) g11<1>F g59<4,1,1>F g27<4,1,1>F g11<4,1,1>F { align16 WE_normal 2Q };\n"
+ "0x00000a00: lrp(8) g20<1>F g56<4,4,1>F g28<4,4,1>F g20<4,4,1>F { align16 WE_normal 1Q };\n"
+ "0x00000a10: lrp(8) g21<1>F g57<4,4,1>F g29<4,4,1>F g21<4,4,1>F { align16 WE_normal 2Q };\n"
+ "0x00000a20: lrp(8) g22<1>F g56<4,4,1>F g30<4,4,1>F g22<4,4,1>F { align16 WE_normal 1Q };\n"
+ "0x00000a30: lrp(8) g23<1>F g57<4,4,1>F g31<4,4,1>F g23<4,4,1>F { align16 WE_normal 2Q };\n"
+ "0x00000a40: lrp(8) g24<1>F g56<4,4,1>F g32<4,4,1>F g24<4,4,1>F { align16 WE_normal 1Q };\n"
+ "0x00000a50: lrp(8) g25<1>F g57<4,4,1>F g33<4,4,1>F g25<4,4,1>F { align16 WE_normal 2Q };\n"
+ "0x00000a60: lrp(8) g26<1>F g56<4,4,1>F g34<4,4,1>F g26<4,4,1>F { align16 WE_normal 1Q };\n"
+ "0x00000a70: lrp(8) g27<1>F g57<4,4,1>F g35<4,4,1>F g27<4,4,1>F { align16 WE_normal 2Q };\n"
+ "0x00000a80: lrp(8) g4<1>F g56<4,4,1>F g12<4,4,1>F g4<4,4,1>F { align16 WE_normal 1Q };\n"
+ "0x00000a90: lrp(8) g5<1>F g57<4,4,1>F g13<4,4,1>F g5<4,4,1>F { align16 WE_normal 2Q };\n"
+ "0x00000aa0: lrp(8) g6<1>F g56<4,4,1>F g14<4,4,1>F g6<4,4,1>F { align16 WE_normal 1Q };\n"
+ "0x00000ab0: lrp(8) g7<1>F g57<4,4,1>F g15<4,4,1>F g7<4,4,1>F { align16 WE_normal 2Q };\n"
+ "0x00000ac0: lrp(8) g8<1>F g56<4,4,1>F g16<4,4,1>F g8<4,4,1>F { align16 WE_normal 1Q };\n"
+ "0x00000ad0: lrp(8) g9<1>F g57<4,4,1>F g17<4,4,1>F g9<4,4,1>F { align16 WE_normal 2Q };\n"
+ "0x00000ae0: lrp(8) g10<1>F g56<4,4,1>F g18<4,4,1>F g10<4,4,1>F { align16 WE_normal 1Q };\n"
+ "0x00000af0: lrp(8) g11<1>F g57<4,4,1>F g19<4,4,1>F g11<4,4,1>F { align16 WE_normal 2Q };\n"
+ "0x00000b00: lrp(8) g4<1>F g58<4,4,1>F g20<4,4,1>F g4<4,4,1>F { align16 WE_normal 1Q };\n"
+ "0x00000b10: lrp(8) g5<1>F g59<4,4,1>F g21<4,4,1>F g5<4,4,1>F { align16 WE_normal 2Q };\n"
+ "0x00000b20: lrp(8) g6<1>F g58<4,4,1>F g22<4,4,1>F g6<4,4,1>F { align16 WE_normal 1Q };\n"
+ "0x00000b30: lrp(8) g7<1>F g59<4,4,1>F g23<4,4,1>F g7<4,4,1>F { align16 WE_normal 2Q };\n"
+ "0x00000b40: lrp(8) g8<1>F g58<4,4,1>F g24<4,4,1>F g8<4,4,1>F { align16 WE_normal 1Q };\n"
+ "0x00000b50: lrp(8) g9<1>F g59<4,4,1>F g25<4,4,1>F g9<4,4,1>F { align16 WE_normal 2Q };\n"
+ "0x00000b60: lrp(8) g10<1>F g58<4,4,1>F g26<4,4,1>F g10<4,4,1>F { align16 WE_normal 1Q };\n"
+ "0x00000b70: lrp(8) g11<1>F g59<4,4,1>F g27<4,4,1>F g11<4,4,1>F { align16 WE_normal 2Q };\n"
"0x00000b80: mov(16) g114<1>F g4<8,8,1>F { align1 WE_normal 1H };\n"
"0x00000b90: mov(16) g116<1>F g6<8,8,1>F { align1 WE_normal 1H };\n"
"0x00000ba0: mov(16) g118<1>F g8<8,8,1>F { align1 WE_normal 1H };\n"
--
1.8.3.2
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