[Mesa-dev] [PATCH 05/13] i965/gen8: Surface state overriding for stencil

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/gen8_surface_state.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 32d1c33..6e6b88a 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -292,8 +292,8 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
    uint32_t surf_type;
    bool is_array = false;
    int depth = MAX2(irb->layer_count, 1);
-   int min_array_element = irb->mt_layer / MAX2(mt->num_samples, 1);
-
+   const int min_array_element = (mt->format == MESA_FORMAT_S_UINT8) ?
+      0 : (irb->mt_layer / MAX2(mt->num_samples, 1));
    GLenum gl_target =
       rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
 
@@ -308,8 +308,12 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
    /* Render targets can't use IMS layout. Stencil in turn gets configured as
     * single sampled and indexed manually by the program.
     */
-   if (mt->format != MESA_FORMAT_S_UINT8)
+   if (mt->format == MESA_FORMAT_S_UINT8) {
+      brw_configure_w_tiled(mt, true, &width, &height, &pitch,
+                            &tiling, &format);
+   } else {
       assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
+   }
 
    switch (gl_target) {
    case GL_TEXTURE_CUBE_MAP_ARRAY:
@@ -360,7 +364,8 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
    if (mt->format != MESA_FORMAT_S_UINT8)
       surf[4] |= gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
 
-   surf[5] = irb->mt_level - irb->mt->first_level;
+   surf[5] = mt->format == MESA_FORMAT_S_UINT8 ?
+                0 : (irb->mt_level - irb->mt->first_level);
 
    surf[6] = 0; /* Nothing of relevance. */
 
-- 
1.8.3.1