[Mesa-dev] [rong.r.yang at intel.com: [Intel-gfx] How user space applications load registers on HSW?]

[Zou, Nanhai]

Hi Daniel,
	We need a solution for this. 
	Without correct L3 config setting, all the OpenCL programs that use SLM will fail.
	We cannot set a default L3 config for all OCL programs, because L3 config for SLM will slowdown kernel that are not using SLM.
	When do you think the command parser could be ready?

Thanks
Zou Nanhai

-----Original Message-----
From: daniel.vetter at ffwll.ch [mailto:daniel.vetter at ffwll.ch] On Behalf Of Daniel Vetter
Sent: Tuesday, May 13, 2014 2:11 PM
To: Yang, Rong R
Cc: Kenneth Graunke; Zou, Nanhai; mesa-dev; Ben Widawsky; intel-gfx
Subject: Re: [Mesa-dev] [rong.r.yang at intel.com: [Intel-gfx] How user space applications load registers on HSW?]

On Mon, May 12, 2014 at 10:02 AM, Yang, Rong R <rong.r.yang at intel.com> wrote:
> Hi, Ken,
>
>     Thanks for your patch.
>     But how do you release your driver on the HSW products? If can't LRI/LRM from userspace batches, almost all of OpenCL application can't run.
>     So if I want to announce that the OpenCL driver support HSW, it must have a way to load L3CTRLREG2 and L3CTRLREG3.

mesa doesn't do L3 control afaik.

> Hi, Ben
>
>     There are only two immediate values need to load L3CTRLREG2 and 
> L3CTRLREG3 to enable and disable SLM. So can I add the flag to exec buffer? when exec buffer receive this flag, load the immediate to L3CTRLREG2 and L3CTRLREG3. Is it acceptable?

I think I'll reject this in the hopes that this will speed up the command parser ...

Thanks, Daniel

>
> Thanks.
>
> -----Original Message-----
> From: Kenneth Graunke [mailto:kenneth at whitecape.org]
> Sent: Wednesday, May 07, 2014 2:57 AM
> To: Yang, Rong R
> Cc: Ben Widawsky; mesa-dev; intel-gfx
> Subject: Re: [Mesa-dev] [rong.r.yang at intel.com: [Intel-gfx] How user 
> space applications load registers on HSW?]
>
> On 05/06/2014 08:26:15 AM, Yang, Rong R wrote:
>> Hi,
>>
>> I am developing the HSW's OCL driver in the linux. I encounter a LRI 
>> problem on HSW.
>>
>>
>> Some gpgpu's applications, which use the shared local memory, must 
>> load the L3CTRLREG2 and L3CTRLREG3 registers to allocate the SLM in 
>> the L3 cache.
>>
>> So I add L3CTRLREG2 and L3CTRLREG3 to the gen7_render_regs to pass 
>> the cmds parse when exec buffer. But it still don't work.
>>
>> I notice that, on HSW, the commands that load the register, such as 
>> MI_LOAD_REGISTER_IMM, will be converted to NOOP by the GPU if the 
>> batch buffer's MI_BATCH_NON_SECURE_HSW bit is set. And after parse 
>> cmd, the MI_BATCH_NON_SECURE_HSW still set in the kernel. So HSW 
>> don't accept LRI commands.
>>
>>
>> Can I load these registers in the user space? Or should I hack the 
>> kernel?
>>
>>
>> Yang Rong
>
> I've been asking the kernel developers for the ability to LRI/LRM from userspace batches for around 1.5 years.  Unfortunately, we're still waiting, and I honestly have no idea when they're going to finish it.
>
> In the meantime, you can apply the attached patch to your kernel tree to disable the hardware scanner, letting you run whatever commands you want.  Obviously, we can't ship this on production systems, but it will allow you to do your development without having to wait for the kernel team.
>
> --Ken
> _______________________________________________
> mesa-dev mailing list
> mesa-dev at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev



--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch