[Mesa-dev] [PATCH 4/4] i965/vec4: Generate better code for ir_triop_csel.
Ian Romanick
idr at freedesktop.org
Thu Oct 16 09:01:42 PDT 2014
On 10/15/2014 08:51 PM, Kenneth Graunke wrote:
> Previously, we generated an extra CMP instruction:
>
> cmp.ge.f0(8) g6<1>D g1<0,4,1>F 0F
> cmp.nz.f0(8) null g6<4,4,1>D 0D
> (+f0) sel(8) g5<1>F g1.4<0,4,1>F g2<0,4,1>F
>
> The first operand is always a boolean, and we want to predicate the SEL
> on that. Rather than producing a boolean value and comparing it against
> zero, we can just produce a condition code in the flag register.
>
> Now we generate:
>
> cmp.ge.f0(8) null g1<0,4,1>F 0F
> (+f0) sel(8) g5<1>F g1.4<0,4,1>F g2<0,4,1>F
>
> No difference in shader-db.
Do any piglit tests generate ir_triop_csel for VS or GS? The change is
nearly identical to the FS change, but it would be nice to know any of
it was exercised.
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> index 93aa533..4c517af 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> @@ -1277,6 +1277,20 @@ vec4_visitor::visit(ir_expression *ir)
> dst_reg result_dst(this, ir->type);
> src_reg result_src(result_dst);
>
> + if (ir->operation == ir_triop_csel) {
> + ir->operands[1]->accept(this);
> + op[1] = this->result;
> + ir->operands[2]->accept(this);
> + op[2] = this->result;
> +
> + enum brw_predicate predicate;
> + emit_bool_to_cond_code(ir->operands[0], &predicate);
> + inst = emit(BRW_OPCODE_SEL, result_dst, op[1], op[2]);
> + inst->predicate = predicate;
> + this->result = result_src;
> + return;
> + }
> +
> for (operand = 0; operand < ir->get_num_operands(); operand++) {
> this->result.file = BAD_FILE;
> ir->operands[operand]->accept(this);
>
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