[Mesa-dev] [PATCH 02/16] i965/skl: Update 3DSTATE_SBE for Skylake.

[Anuj Phogat]

On Wed, Sep 24, 2014 at 12:28 PM, Kristian Høgsberg <krh at bitplanet.net> wrote:
> From: Damien Lespiau <damien.lespiau at intel.com>
>
> This commands has seen the addition of 2 dwords that allow to specify
> which channels of which attributes need to be forwarded to the fragment
> shader.
>
> v2: Rebase forward a year (done by Ken).
>
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
> ---
>  src/mesa/drivers/dri/i965/brw_defines.h   |  6 ++++++
>  src/mesa/drivers/dri/i965/gen8_sf_state.c | 30 ++++++++++++++++++++++++++++--
>  2 files changed, 34 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
> index b2216fe..aca78af 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -1903,6 +1903,12 @@ enum brw_message_target {
>  /* DW12: attr 0-7 wrap shortest enables */
>  /* DW13: attr 8-16 wrap shortest enables */
>
> +/* DW5-6: Attribute active components (gen9) */
Aren't they DW4-5?

> +#define GEN9_SBE_ACTIVE_COMPONENT_NONE                 0
> +#define GEN9_SBE_ACTIVE_COMPONENT_XY                   1
> +#define GEN9_SBE_ACTIVE_COMPONENT_XYZ                  2
> +#define GEN9_SBE_ACTIVE_COMPONENT_XYZW                 3
> +
>  #define _3DSTATE_SBE_SWIZ                       0x7851 /* GEN8+ */
>
>  #define _3DSTATE_RASTER                         0x7850 /* GEN8+ */
> diff --git a/src/mesa/drivers/dri/i965/gen8_sf_state.c b/src/mesa/drivers/dri/i965/gen8_sf_state.c
> index 4263eaf..05e5a2e 100644
> --- a/src/mesa/drivers/dri/i965/gen8_sf_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_sf_state.c
> @@ -39,10 +39,13 @@ upload_sbe(struct brw_context *brw)
>     uint32_t urb_entry_read_length;
>     uint32_t point_sprite_enables;
>     uint32_t flat_enables;
> +   int sbe_cmd_length;
>
>     uint32_t dw1 =
>        GEN7_SBE_SWIZZLE_ENABLE |
>        num_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT;
> +   uint32_t dw4 = 0;
> +   uint32_t dw5 = 0;
>
>     /* _NEW_BUFFERS */
>     bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
> @@ -79,11 +82,34 @@ upload_sbe(struct brw_context *brw)
>        GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH |
>        GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET;
>
> -   BEGIN_BATCH(4);
> -   OUT_BATCH(_3DSTATE_SBE << 16 | (4 - 2));
> +   if (brw->gen == 8) {
> +      sbe_cmd_length = 4;
> +   } else {
> +      sbe_cmd_length = 6;
> +
> +      /* prepare the active component dwords */
> +      int input_index = 0;
> +      for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
> +         if (!(brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(attr)))
> +            continue;
> +
> +         if (input_index < 16)
> +            dw4 |= (GEN9_SBE_ACTIVE_COMPONENT_XYZW << (input_index << 1));
> +         else
> +            dw5 |= (GEN9_SBE_ACTIVE_COMPONENT_XYZW << (input_index << 1));
> +
> +         ++input_index;
> +      }
> +   }
> +   BEGIN_BATCH(sbe_cmd_length);
> +   OUT_BATCH(_3DSTATE_SBE << 16 | (sbe_cmd_length - 2));
>     OUT_BATCH(dw1);
>     OUT_BATCH(point_sprite_enables);
>     OUT_BATCH(flat_enables);
> +   if (sbe_cmd_length >= 6) {
> +      OUT_BATCH(dw4);
> +      OUT_BATCH(dw5);
> +   }
>     ADVANCE_BATCH();
>
>     BEGIN_BATCH(11);
> --
> 2.1.0
>
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