[Mesa-dev] [PATCH 42/41] i965: Fix widths on gen5 math instructions.

[Jason Ekstrand]

This commit uses a 16-wide MRF instead of a hardware register when setting
up math instructions and properly sets the base_mrf on the second emitted
instruction.
---
 src/mesa/drivers/dri/i965/brw_fs.cpp           | 2 +-
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 143b590..af9736b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1648,7 +1648,7 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
       fs_reg &op0 = is_int_div ? src1 : src0;
       fs_reg &op1 = is_int_div ? src0 : src1;
 
-      emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + 1, op1.type), op1);
+      emit(MOV(fs_reg(MRF, base_mrf + 1, op1.type, dispatch_width), op1));
       inst = emit(opcode, dst, op0, reg_null_f);
 
       inst->base_mrf = base_mrf;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 59c7e7c..485c050 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -346,7 +346,7 @@ fs_generator::generate_math_gen4(fs_inst *inst,
       brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
       gen4_math(p, firsthalf(dst),
 	        op,
-	        inst->base_mrf + 1, firsthalf(src),
+	        inst->base_mrf, firsthalf(src),
 	        BRW_MATH_DATA_VECTOR,
 	        BRW_MATH_PRECISION_FULL);
       brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
-- 
2.1.0