[Mesa-dev] [PATCH 06.5/41] SQUAHS: i965/fs: Always 2-align registers SIMD16 for gen <= 5

[Matt Turner]

On Fri, Sep 26, 2014 at 12:24 PM, Jason Ekstrand <jason at jlekstrand.net> wrote:
> ---
>  src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 61 ++++++++++++++++++-----
>  1 file changed, 48 insertions(+), 13 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
> index 567f8e2..8d96906 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
> @@ -117,7 +117,21 @@ brw_alloc_reg_set(struct intel_screen *screen, int reg_width)
>     /* Compute the total number of registers across all classes. */
>     int ra_reg_count = 0;
>     for (int i = 0; i < class_count; i++) {
> -      ra_reg_count += base_reg_count - (class_sizes[i] - 1);
> +      if (devinfo->gen <= 5 && reg_width == 2) {
> +         /* From the GM5 PRM:

G45

I think I want you to explain how this works at the office today.