[Mesa-dev] [PATCH 5/6] i965/fs: Implement SIMD16 64-bit integer multiplies on Gen 7.
Matt Turner
mattst88 at gmail.com
Sun Sep 28 13:26:33 PDT 2014
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index e6c34fa..ff1b533 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -658,13 +658,10 @@ fs_visitor::visit(ir_expression *ir)
}
break;
case ir_binop_imul_high: {
- if (brw->gen == 7)
- no16("SIMD16 explicit accumulator operands unsupported\n");
-
struct brw_reg acc = retype(brw_acc_reg(), this->result.type);
fs_inst *mul = emit(MUL(acc, op[0], op[1]));
- emit(MACH(this->result, op[0], op[1]));
+ fs_inst *mach = emit(MACH(this->result, op[0], op[1]));
/* Until Gen8, integer multiplies read 32-bits from one source, and
* 16-bits from the other, and relying on the MACH instruction to
@@ -686,6 +683,15 @@ fs_visitor::visit(ir_expression *ir)
}
}
+ if (brw->gen == 7 && dispatch_width == 16) {
+ mul->force_uncompressed = true;
+ mach->force_uncompressed = true;
+
+ mul = emit(MUL(acc, half(op[0], 1), half(op[1], 1)));
+ mul->force_sechalf = true;
+ mach = emit(MACH(half(this->result, 1), half(op[0], 1), half(op[1], 1)));
+ mach->force_sechalf = true;
+ }
break;
}
case ir_binop_div:
--
1.8.5.5
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