[Mesa-dev] [PATCH] i965: Always use Y-tiled buffers on SKL+

[Daniel Vetter]

On Sat, Apr 11, 2015 at 01:16:11PM -0700, Ben Widawsky wrote:
> Starting with Skylake, the display engine is capable of scanning out from
> Y-tiled buffers. As such, we can and should use Y-tiling for better efficiency.
> 
> Note that the buffer allocation done for mipmaps will already never allocate an
> X-tiled buffer for GEN9.
> 
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>

You need a recent enough ddx to make use of Y-tiled buffers, which atm
still doesn't yet exist. This would at least need some kind of handshake
with the compositor to make sure it understands this, presuming I didn't
miss something.

> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c |  4 ++++
>  src/mesa/drivers/dri/i965/intel_screen.c      | 21 ++++++++++++++++++---
>  2 files changed, 22 insertions(+), 3 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index eb226d5..4408ac9 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -142,6 +142,10 @@ intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
>        *height = 4;
>        break;
>     case I915_TILING_X:
> +      /* The docs are somewhat confusing with the way the tables are displayed.
> +       * However, it does clearly state: "MCS and Lossless compression is
> +       * supported for TiledY/TileYs/TileYf non-MSRTs only." */
> +      assert(brw->gen < 9);
>        *width_px = 64 / mt->cpp;
>        *height = 2;
>     }
> diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
> index cb9710f..06f0a06 100644
> --- a/src/mesa/drivers/dri/i965/intel_screen.c
> +++ b/src/mesa/drivers/dri/i965/intel_screen.c
> @@ -510,7 +510,11 @@ intel_create_image(__DRIscreen *screen,
>     int cpp;
>     unsigned long pitch;
>  
> -   tiling = I915_TILING_X;
> +   if (intelScreen->devinfo->gen >= 9) {
> +      tiling = I915_TILING_Y;
> +   } else {
> +      tiling = I915_TILING_X;
> +   }
>     if (use & __DRI_IMAGE_USE_CURSOR) {
>        if (width != 64 || height != 64)
>  	 return NULL;
> @@ -1101,8 +1105,14 @@ intel_detect_swizzling(struct intel_screen *screen)
>     drm_intel_bo *buffer;
>     unsigned long flags = 0;
>     unsigned long aligned_pitch;
> -   uint32_t tiling = I915_TILING_X;
>     uint32_t swizzle_mode = 0;
> +   uint32_t tiling;
> +
> +   if (screen->devinfo->gen >= 9) {
> +      tiling = I915_TILING_Y;
> +   } else {
> +      tiling = I915_TILING_X;
> +   }

Unneeded change (swizzling doesn't change between X and Y tiled) and gen9+
is hardcoded to unswizzled in the hw anyway.
-Daniel

>  
>     buffer = drm_intel_bo_alloc_tiled(screen->bufmgr, "swizzle test",
>  				     64, 64, 4,
> @@ -1409,7 +1419,12 @@ intelAllocateBuffer(__DRIscreen *screen,
>        return NULL;
>  
>     /* The front and back buffers are color buffers, which are X tiled. */
> -   uint32_t tiling = I915_TILING_X;
> +   uint32_t tiling;
> +   if (intelScreen->devinfo->gen >= 9) {
> +      tiling = I915_TILING_Y;
> +   } else {
> +      tiling = I915_TILING_X;
> +   }
>     unsigned long pitch;
>     int cpp = format / 8;
>     intelBuffer->bo = drm_intel_bo_alloc_tiled(intelScreen->bufmgr,
> -- 
> 2.3.5
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch