[Mesa-dev] [PATCH 16/18] i965/ps/gen7: Refactor state uploading
Topi Pohjolainen
topi.pohjolainen at intel.com
Wed Apr 22 13:47:36 PDT 2015
Now the uploading depends only on the input parameters instead
of consulting the current gl-state.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_state.h | 9 +++++
src/mesa/drivers/dri/i965/gen7_wm_state.c | 58 ++++++++++++++++++++-----------
2 files changed, 46 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 5be8035..178f039 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -245,6 +245,15 @@ void brw_update_renderbuffer_surfaces(struct brw_context *brw,
uint32_t render_target_start,
uint32_t *surf_offset);
+/* gen7_wm_state.c */
+void
+gen7_upload_ps_state(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_stage_state *stage_state,
+ const struct brw_wm_prog_data *prog_data,
+ bool enable_dual_src_blend, unsigned sample_mask,
+ unsigned fast_clear_op);
+
/* gen7_wm_surface_state.c */
uint32_t gen7_surface_tiling_mode(uint32_t tiling);
uint32_t gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout l);
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 923414e..dc4264c 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -122,21 +122,23 @@ const struct brw_tracked_state gen7_wm_state = {
.emit = upload_wm_state,
};
-static void
-upload_ps_state(struct brw_context *brw)
+void
+gen7_upload_ps_state(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_stage_state *stage_state,
+ const struct brw_wm_prog_data *prog_data,
+ bool enable_dual_src_blend, unsigned sample_mask,
+ unsigned fast_clear_op)
{
struct gl_context *ctx = &brw->ctx;
uint32_t dw2, dw4, dw5, ksp0, ksp2;
const int max_threads_shift = brw->is_haswell ?
HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
- /* BRW_NEW_FS_PROG_DATA */
- const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
-
dw2 = dw4 = dw5 = ksp2 = 0;
- dw2 |=
- (ALIGN(brw->wm.base.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
+ dw2 |= ((ALIGN(stage_state->sampler_count, 4) / 4) <<
+ GEN7_PS_SAMPLER_COUNT_SHIFT);
dw2 |= ((prog_data->base.binding_table.size_bytes / 4) <<
GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
@@ -148,7 +150,7 @@ upload_ps_state(struct brw_context *brw)
* in 3DSTATE_SAMPLE_MASK; the values should match. */
/* _NEW_BUFFERS, _NEW_MULTISAMPLE */
if (brw->is_haswell)
- dw4 |= SET_FIELD(gen6_determine_sample_mask(brw), HSW_PS_SAMPLE_MASK);
+ dw4 |= SET_FIELD(sample_mask, HSW_PS_SAMPLE_MASK);
dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
@@ -181,16 +183,11 @@ upload_ps_state(struct brw_context *brw)
else
dw4 |= GEN7_PS_POSOFFSET_NONE;
- /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR
- *
- * The hardware wedges if you have this bit set but don't turn on any dual
+ /* The hardware wedges if you have this bit set but don't turn on any dual
* source blend factors.
*/
- if (prog_data->dual_src_blend &&
- (ctx->Color.BlendEnabled & 1) &&
- ctx->Color.Blend[0]._UsesDualSrc) {
+ if (enable_dual_src_blend)
dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
- }
/* BRW_NEW_FS_PROG_DATA */
if (prog_data->num_varying_inputs != 0)
@@ -202,7 +199,7 @@ upload_ps_state(struct brw_context *brw)
* better performance than 'SIMD8 only' dispatch.
*/
int min_inv_per_frag =
- _mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false);
+ _mesa_get_min_invocations_per_fragment(ctx, fp, false);
assert(min_inv_per_frag >= 1);
if (prog_data->prog_offset_16 || prog_data->no_8) {
@@ -213,22 +210,22 @@ upload_ps_state(struct brw_context *brw)
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
dw5 |= (prog_data->dispatch_grf_start_reg_16 <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
- ksp0 = brw->wm.base.prog_offset;
- ksp2 = brw->wm.base.prog_offset + prog_data->prog_offset_16;
+ ksp0 = stage_state->prog_offset;
+ ksp2 = stage_state->prog_offset + prog_data->prog_offset_16;
} else {
dw5 |= (prog_data->dispatch_grf_start_reg_16 <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
- ksp0 = brw->wm.base.prog_offset + prog_data->prog_offset_16;
+ ksp0 = stage_state->prog_offset + prog_data->prog_offset_16;
}
}
else {
dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
dw5 |= (prog_data->base.dispatch_grf_start_reg <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
- ksp0 = brw->wm.base.prog_offset;
+ ksp0 = stage_state->prog_offset;
}
- dw4 |= brw->wm.fast_clear_op;
+ dw4 |= fast_clear_op;
BEGIN_BATCH(8);
OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
@@ -248,6 +245,25 @@ upload_ps_state(struct brw_context *brw)
ADVANCE_BATCH();
}
+static void
+upload_ps_state(struct brw_context *brw)
+{
+ /* BRW_NEW_FS_PROG_DATA */
+ const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
+ const struct gl_context *ctx = &brw->ctx;
+ /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR */
+ const bool enable_dual_src_blend = prog_data->dual_src_blend &&
+ (ctx->Color.BlendEnabled & 1) &&
+ ctx->Color.Blend[0]._UsesDualSrc;
+ /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
+ const unsigned sample_mask =
+ brw->is_haswell ? gen6_determine_sample_mask(brw) : 0;
+
+ gen7_upload_ps_state(brw, brw->fragment_program, &brw->wm.base, prog_data,
+ enable_dual_src_blend, sample_mask,
+ brw->wm.fast_clear_op);
+}
+
const struct brw_tracked_state gen7_ps_state = {
.dirty = {
.mesa = _NEW_BUFFERS |
--
1.9.3
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